4.3 Cache maintenance operations

The CCN-502 uses several CHI Cache Maintenance Operations (CMOs).

The following operations are supported:

These operations always look up the L3 cache and the snoop filter, and take the following actions:


If the CMO is MakeInvalid, there is no writeback to the memory controller.

In addition, the L3 cache and snoop filter can be flushed or invalidated by using the power state mechanisms that are described here. For example, the L3 cache can be flushed (cleaned and invalidated) by transitioning from FAM→SFONLY power state, by writing to all instances of the HN-F P-state Request register. Both the L3 and snoop filter can be flushed by transitioning from FAM→NOL3.

The snoop filter does not track RN-F coherence while the HN-F is in NOL3 state, so the RN-F caches must be flushed before transitioning from NOL3 to SFONLY, HAM, or FAM states.


The system must ensure that no P-Channel interface initiated power transitions are in progress, when writes to the HN-F P-state registers occur.
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