6.3.1 Cache performance

Cache performance events are required to calculate the cache miss rate and the cache allocation.

The following sections describe the cache performance events.

Cache miss rate

The cache events that are required to calculate the cache miss rate are:

PMU_HN_CACHE_MISS_EVENTCounts the total cache misses. This is a first-time lookup result, and is high priority.
PMU_HNL3_SF_CACHE_ACCESS_EVENTThe total number of cache accesses. These are first-time accesses, and are high priority.

Note:

The performance counter architecture enables only four HNs to collect the cache miss rate. However, due to the CCN-502 microarchitecture, the cache miss rate that is measured at one HN-F is a good proxy for the cache miss rate of the remaining HN-Fs.

Calculate the cache miss rate as follows:

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Certain request types can cause multiple cache accesses:

  • Lookup.
  • Tag update.
  • Victim selection.
  • Cache fill.

Event counting is therefore limited to first time accesses only. For example, for a ReadUnique transaction that leads to an L3 hit, PMU_HN_CACHE_ACCESS_EVENT is only counted the first time a cache lookup is performed. The tag update is not counted as a cache access. Similarly, for WriteBack or Write*Unique transactions with an L3 allocate hint, only the first instance of an L3 lookup is counted as an access and hit or miss. The eventual victim selection and cache fill are not counted as additional accesses.

Cache allocations

The cache allocation event counts the number of times an HN-F L3 cache is allocated. It provides an approximate cache usage for this particular application over a specific time slice. This event does not check whether the application has any hot sets.

PMU_HN_CACHE_FILL_EVENTCounts all cache line allocations to L3 cache.

All cache line writes, that is, Write*Unique, WriteBack, and Evictions that are allocated in L3 cache, are counted towards this event.

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