6.1 Performance optimization guidelines

There are some restrictions when optimizing the CCN-502.

To obtain maximum performance from the CCN-502, the system integrator must be aware of the following information:


When ordering is not required, transaction requests must be dispatched with non-overlapping IDs to ensure optimal bandwidth operation. Large burst transactions, that is, larger than 64B, must be split into 64B or smaller burst transactions. In addition, set AxSIZE to 4 (16B) to fully utilize the available bandwidth.

Set the WriteUnique Optimization (wuo) configuration register bit to optimize performance for ordered WriteUnique streaming operations.


  • In systems where a PCIe Root Complex (RC) is present, the wuo bit must be set in the RN-I instance that connects to the RC and only in that RN-I instance. Clear the wuo bit in the other RN-I instances.
  • When the wuo bit is set, WriteNoSnp operations targeting the same HN partition are ordered even when their IDs are non-overlapping.

Read or write requests to different parts of the same cache line must be combined into a single cache line request. For example, multiple (partial) WriteUnique transactions must be combined into a single WriteUnique or a single WriteLineUnique transaction, where all bytes in the cache line are written.

All transactions that the RN-I sends to the HN-I have the CHI ReqOrder bit set, and the maximum achievable bandwidth is affected accordingly.

HN-F,HN-IHigh temporal locality of address usage in transactions can cause same-address dependencies to occur in the event of transactions with addresses to overlapping cache lines. This results in higher latency because of serialization delays between these transactions. The CCN-502 is microarchitected to avoid hotspotting in the HN-F partitions or in the memory controllers, but this is unavoidable in cases of temporally-local same-address usage.
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