A.5 Interrupt and event signals

The following table shows the interrupt and event signals.

Table A-17 Interrupt and event signals

Signal Type Description Connection information
INTREQ Output Debug trigger and error indicator. Indicates error or performance monitor counter overflow. Connect to external interrupt control logic or interrupt controller.

CLREXMONREQ_NID<x>

Where <x> is 1, 5, 7, or 11 (6XP/2HNF) or <x> is 1, 7, 9, or 15 (8XP/4HNF).

Output Indicates that an exclusive monitor in the CCN-502 has been cleared. Paired with the corresponding CLREXMONACK_NID<x> input pin in an asynchronous-safe 4-phase handshake. For connection to ARMv8-compliant processors only. Connect to CLREXMON control logic for processor at Node ID <x>.

CLREXMONACK_NID<x>

Where <x> is 1, 5, 7, or 11 (6XP/2HNF) or <x> is 1, 7, 9, or 15 (8XP/4HNF).

Input Acknowledgment from an ARMv8-compliant processor that a corresponding CLREXMONREQ has been received. Paired with the corresponding CLREXMONREQ_NID<x> output pin in an asynchronous-safe 4-phase handshake. Connect to CLREXMON control logic for processor at Node ID <x> or tie LOW if processor not populated or not ARMv8-compliant.
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