A.10 Debug, trace, and PMU interface signals

Signals that aid debugging are included in the CCN-502.

The following table shows the debug, trace, and PMU interface signals.

Table A-56 Debug, trace, and PMU interface signals

Signal Type Description Connection information
DCLKEN Input Debug clock enable, which controls the clock for the STMHWEVENT interface. DCLKEN must be synchronous to GCLK0 and an integer ratio between 2:1 and 4:1 of GCLK0. Connect to clock enable logic.
STMHWEVENT[31:0] Output Trace output from Debug Event Module (DEM). Indication of watchpoint match events. Connect to Hardware Event Observability Interface of System Trace Macrocell (STM).
DBGWATCHTRIGREQ Output Trigger output from DEM indicating assertion of a DT event. DBGWATCHTRIGREQ is asynchronous-safe, and operates in a 4-phase handshake with DBGWATCHTRIGACK. Connect to external debug and trace control logic.
DBGWATCHTRIGACK Input External acknowledgment of receipt of DBGWATCHTRIGREQ. DBGWATCHTRIGACK must be asynchronous-safe, and operates in a 4-phase handshake with DBGWATCHTRIGREQ. Connect to external debug and trace control logic, or tie LOW if DBGWATCHTRIGREQ is unused.
PMUSNAPSHOTREQ Input External request that the live PMU counters are snapshotted to the shadow registers. PMUSNAPSHOTREQ must be asynchronous-safe, and operates in a 4-phase handshake with PMUSNAPSHOTACK. Connect to external debug and trace control logic, or tie LOW if unused.
PMUSNAPSHOTACK Output Indication that all live PMU counters have been copied to shadow registers and the contents can be read. PMUSNAPSHOTACK is asynchronous-safe, and operates in a 4-phase handshake with PMUSNAPSHOTREQ. Connect to external debug and trace control logic.
NIDEN Input Global enable for all debug, trace, and PMU functionality.
0Disabled.
1Enabled.
Tie or drive as appropriate to meet system security requirements.
SPNIDEN Input

Global enable for secure debug, trace, and PMU capability. Only applicable when NIDEN is enabled.

0Disabled.
1Enabled.
Non-ConfidentialPDF file icon PDF versionARM 100052_0001_00_en
Copyright © 2014, 2015, 2017 ARM Limited or its affiliates. All rights reserved.