|Non-Confidential||PDF version||ARM 100052_0001_00_en|
|Home > Signal Descriptions > DFT and MBIST interface signals|
The following table shows the Design For Test (DFT) signals.
Table A-57 DFT signals
|DFTCLKBYPASS||Input||Select the L3 RAM clock to follow the CCN-502 input clock, as applicable for each clock region.||Tie LOW if unused.|
|DFTRAMHOLD||Input||Disable the RAM chip select during scan shift.|
|DFTMCPHOLD||Input||Assert to prevent HN-F multicycle RAMs from clocking during capture cycles.|
|DFTRSTDISABLE||Input||Disable internal synchronized reset during scan shift.|
|DFTSE||Input||Scan shift enable, forces on the clock grids during scan shift.|
During functional mode, the HN-F L3 and SF RAM set address and write data inputs satisfy RAM hold timing constraints using pipeline behavior. The set address and write data are only clocked and enabled the cycle before the RAMs are accessed, and are held the cycle that the RAM clock asserts.
The RAM hold constraints are not guaranteed during ATPG test, because random data is shifted into the flops that control the set address and write data flop enables. This allows the set address and write data to change in the same cycle as a RAM access, violating the RAM hold constraints.
This signal addresses the hold constraints during ATPG test. It is used to force the RAM set address and write data flop enables LOW in the cycle that RAM clocks are enabled during ATPG test.
The combination of the functional pipeline behavior and this override logic, enables hold MCPs to be used on the RAM set address and write data inputs in the implementation flow and during static timing analysis.
The following table shows the Memory Built-in Self Test (MBIST) signals.
Table A-58 MBIST signals
|nMBISTRESET||Input||Primary reset to enter MBIST. Must be HIGH during functional non-MBIST operation.||Tie HIGH if unused.|
|MBISTREQ||Input||L3 MBIST mode request.||Tie LOW if unused.|