4.11 OCM

On-Chip Memory (OCM) allows for the creation of CCN systems without physical DDR memory.

In OCM mode, the CCN-502 does not send requests to the SN‑F provided the following requirements are met:

Note:

If any of these requirements are not met, the system must be able to generate correct responses for any requests that target the SN‑F.

In OCM mode, cache maintenance operations terminate in the L3. CleanInvalid and CleanShared CMOs terminate in the L3 without performing a WriteBack to the SN‑F. MakeInvalid invalidates the L3 cacheline, and can be used to invalidate the OCM region.

The CCN-502 operates in OCM mode when the hnf_ocm_en bit is set to 1, in the HN‑F Auxiliary Control register. If the hnf_ocm_allways_en bit is set to 1, then all transactions targeting the HN‑Fs have OCM behavior. The OCM region must be contiguous and aligned to the total L3 size of the configuration when hnf_ocm_allways_en is set to 1. If the hnf_ocm_allways_en bit is 0, the OCM regions are defined by the region locking registers that 4.8 Software configurable memory region locking describes.

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