This section describes key CCN-502 features.
The CCN-502 provides the following key
- Dual simplex ring-bus interconnect topology consisting of 6 or 8 crosspoints, with each crosspoint supporting up to two device ports.
- Support for up to 4 fully coherent processor compute clusters.
- Support for up to four memory controllers.
- Support for up to 9 ACE-Lite/ACE-Lite+DVM/AXI4 I/O master devices. Additional devices can be supported using an additional level of interconnect hierarchy, such as the CoreLink NIC-400 Network Interconnect.
- Byte-level odd parity protection on all datapaths.
- Byte-level odd parity generation for data produced by the coherent compute clusters and the L3 cache.
- Broadcast snoop channel.
- DVM message transport between masters.
- QoS regulation for shaping traffic profiles.
- A Performance Monitoring Unit (PMU) to count performance-related events.
- High-performance distributed system cache, 0KB, 256KB, 512KB, 1MB, 2MB, 4MB, or 8MB in capacity, consisting of two or four partitions, each 0KB, 128KB, 512KB, 1MB, or 2MB in capacity. The system cache includes an integrated Point-of-Serialization (PoS) and Point-of-Coherency (PoC) and can be used both for compute and I/O caching.
- Snoop filter (SF) capable of covering 1MB, 2MB, 4MB, 8MB, or 16MB of 64-byte cache-line tags for increased coherency scalability. The SF consists of two or four partitions, each covering either 512KB, 2MB, or 4MB of 64-byte cache-line tags.
- One I/O Home Node with an ACE-Lite or AXI4 master port.
- Error signal gathering using an error bus, with a single point of interrupt coordination on errors.
- 40-bit physical address support
- On-Chip Memory (OCM), which allows for systems without physical memory. The CCN-502 does not access the SN-F, under specific use cases.