Appendix B Revisions

This appendix describes the technical changes between released issues of this book.

B.1 Revisions

Differences between released versions of the document are listed in this appendix.

Table B-1 Issue 0000-00

Change Location Affects
First release - -

Table B-2 Differences between issue 0000-00 and issue 0000-01

Change Location Affects
Added L3 latency entry. Table 1-1 Configurable parameters All revisions
Error handling protocol change. 2.9.2 Error detection, signaling, and reporting
Updated the Error class=0b01 definition. Table 2-2 Error classification field encoding
Added 3 SN content. 3 SN-F memory striping
Added the hnf_ocm_allways_en and hnf_ocm_en bits. HN-F Auxiliary Control register
Updated the dbg_id field reset value. Debug Identification register
Updated the cntcfg field description. PMU Control register
Updated L3 memory system feature list. 4.1 About the L3 memory system
Updated the description for software control of a snapshot request. 5.4.3 DEM PMU capabilities
Updated the description to enable the PMU counter snapshot. 5.7 Example PMU setup
Updated PACTIVE_SF description. Table A-11 Power management signals for snoop filter RAM power domain
Updated PACTIVE_L3RAM0 description. Table A-13 Power management signals for L3 tag/data RAMs way[7:0]
Updated PACTIVE_L3RAM1 description. Table A-15 Power management signals for L3 tag/data RAMs way[15:8]

Table B-3 Differences between issue 0000-01 and issue 0000-02

Change Location Affects
Added information about the use of a hash function and memory aliasing. 3 SN-F memory striping All revisions
Removed support for the OFF→NOL3 power state transition and support for the transition to the OFF power state when nSRESET deasserts.
Updated the Region and Region base address for the RN-Is. Table 3-2 Node register regions
Updated reset value of the hn_cfg_three_sn_en bit. HN-F SAM Control register
Added the hn_cfg_sam_top_address_bit1 and hn_cfg_sam_top_address_bit0 fields.
Updated the bits[11:10] reset values.

Table B-4 Differences between issue 0000-02 and issue 0001-00

Change Location Affects
Added the byte-level odd parity features. 1.3 Features All revisions
Added the number of outstanding DVM snoops that an RN-F can issue. 2.7 DVM messages
Added optional step to reenable the INTREQ interrupt. For the error handling software on detection of assertion of INTREQ
Updated the values for the 10, 12, and 2 and 12, 2, and 4 choices. Table 2-6 3 SN striping values
Added Number of domains for the 8XP/4HNF option. Table 2-7 Clock domain options
Updated the register description Error Interrupt Status register
Corrected the reset value. DVM Domain Control register
Added the possible bit values for the error types.
Added the dat_parity_resperr_disable bit. Auxiliary Control register, XP
Added the pois_dis and par_err_dis bits. HN-F Configuration Control register
Add the par_err_id bit. Error Syndrome 0 register, L3 cache
Added the err_srcid and err_optype fields. Error Syndrome 1 register, L3 cache
Updated the hnf_honor_ewa_description Table 3-99 hnf_aux_ctl register bit assignments
Added byte parity information.
Added programming information for when the HN-I is not the final Point-of-Serialization (PoS). 3.4.2 Programming requirements for designs with an alternative path to the HN-I memory space
Updated the QoS value range values. Table 4-1 QoS classes
Increased the width of the WUSER_S, RUSER_S, WUSER_M, and RUSER_M signals. A.9.1 ACE-Lite-with-DVM slave interface signals
Updated footnotes with information about the HN-I data width. A.9.2 AXI4/ACE-Lite master interface signals
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