ARM® CoreLink™ CCN-502 Cache Coherent Network Technical Reference Manual

Revision r0p1

Table of Contents

About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback on this product
Feedback on content
1 Introduction
1.1 About the CCN-502 Cache Coherent Network
1.2 Compliance
1.3 Features
1.4 Interfaces
1.5 Configurable options
1.5.1 Configurable parameters
1.5.2 Static parameters
1.5.3 Tie-off signals
1.6 Test features
1.7 Product documentation and design flow
1.8 Product revisions
2 Functional Description
2.1 About the functions
2.1.1 Crosspoint
2.1.2 Fully-coherent Home Node
2.1.3 I/O-coherent Requesting Node bridge
2.1.4 I/O Home Node
2.1.5 CHI to AXI bridge
2.1.6 Miscellaneous Node
2.1.7 Power/Clock Control Block
2.1.8 System Address Map overview
2.1.9 Debug Event Module overview
2.1.10 QoS regulator
2.1.11 Optional components
2.2 System configurations
2.3 Addressing capabilities
2.4 Exclusive accesses
2.4.1 HN-F exclusive accesses
2.4.2 HN-I exclusive accesses
2.5 Quality of Service
2.5.1 Architectural QoS support
2.5.2 Microarchitectural QoS support
2.6 Barriers
2.7 DVM messages
2.8 PCIe integration
2.8.1 PCIe master and slave restrictions and requirements
2.8.2 System requirements
2.8.3 HN-I programming sequence
2.9 Error handling
2.9.1 Error types
2.9.2 Error detection, signaling, and reporting
2.9.3 Error handling requirements
2.10 Debug and PMU
2.11 Node ID mapping
2.12 System Address Map
2.12.1 CCN-502 address map
2.12.2 SAM configuration
2.12.3 RN SAM address hash function
2.12.4 HN-F SAM
2.13 Clocking and resets
2.13.1 Clocking
2.13.2 Reset
2.14 Power and clock management
2.14.1 High-level clock gating
2.14.2 Power domains
2.14.3 Power states
2.14.4 P-Channel
2.14.5 L3 data RAM retention control
2.15 Link layer
2.16 Data integrity
2.16.1 Parity error reporting, poisoning, and logging
2.16.2 Byte parity error injection
3 Programmers Model
3.1 About the programmers model
3.1.1 Node configuration register address mapping
3.1.2 Node type IDs
3.1.3 Requirements of configuration register reads and writes
3.2 Register summary
3.3 Register descriptions
3.3.1 MN register descriptions
3.3.2 XP register descriptions
3.3.3 HN-F register descriptions
3.3.4 HN-I register descriptions
3.3.5 Debug event module register descriptions
3.3.6 RN-I bridge register descriptions
3.3.7 SBSX register descriptions
3.4 Programming the CCN-502
3.4.1 Boot-time programming requirements
3.4.2 Programming requirements for designs with an alternative path to the HN-I memory space
3.4.3 Runtime programming requirements
4 L3 Memory System
4.1 About the L3 memory system
4.2 Configurable options
4.3 Cache maintenance operations
4.4 Cacheable and Non-cacheable exclusives
4.5 TrustZone® technology support
4.6 Snoop connectivity and control
4.7 QoS features
4.7.1 QoS decoding
4.7.2 QoS class and POCQ resource availability
4.8 Software configurable memory region locking
4.9 Performance monitoring events
4.10 Error reporting and software configured error injection
4.10.1 Software-configurable error injection
4.10.2 Single-bit ECC error tracking and interrupt
4.11 OCM
5 Debug
5.1 About debug
5.2 Debug Watchpoint Module
5.3 Debug and Trace Bus
5.4 Debug Event Module
5.4.1 DEM trigger capabilities
5.4.2 DEM trace capabilities
5.4.3 DEM PMU capabilities
5.5 Security and DT enable
5.6 Watchpoint setup
5.7 Example PMU setup
6 Performance Optimization and Monitoring
6.1 Performance optimization guidelines
6.2 About the Performance Monitoring Unit
6.2.1 Cycle counter
6.3 HN-F performance events
6.3.1 Cache performance
6.3.2 HN-F counters
6.3.3 Snoop filter events
6.3.4 System-wide events
6.3.5 Quality of Service
6.3.6 HN-F PMU event summary
6.4 RN-I performance events
6.4.1 Bandwidth at RN-I bridges
6.4.2 Bottleneck analysis at RN-I bridges
6.4.3 RN-I PMU event summary
6.5 SBSX and HN-I performance events
6.5.1 Bandwidth at SBSX and HN-I bridges
6.5.2 Bottleneck analysis at SBSX and HN-I bridges
6.5.3 SBSX and HN-I PMU event summary
6.6 Ring performance events
A Signal Descriptions
A.1 About the signal descriptions
A.2 Clock and reset signals
A.3 Clock management signals
A.4 Power management signals
A.5 Interrupt and event signals
A.6 Configuration input signals
A.7 Device population signals
A.8 CHI interface signals
A.8.1 Per-device interface definition
A.8.2 Per-channel interface signals
A.8.3 Non-channel-specific interface signals
A.9 ACE-Lite and AXI interface signals
A.9.1 ACE-Lite-with-DVM slave interface signals
A.9.2 AXI4/ACE-Lite master interface signals
A.10 Debug, trace, and PMU interface signals
A.11 DFT and MBIST interface signals
B Revisions
B.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
0000-00 01 October 2014 Confidential First release for r0p0
0000-01 06 February 2015 Confidential Second release for r0p0
0000-02 05 May 2015 Confidential Third release for r0p0
0001-00 29 August 2017 Non-Confidential First release for r0p1

Non-Confidential Proprietary Notice

This document is protected by copyright and other related rights and the practice or implementation of the information contained in this document may be protected by one or more patents or pending patent applications. No part of this document may be reproduced in any form by any means without the express prior written permission of ARM. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this document unless specifically stated.

Your access to the information in this document is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations infringe any third party patents.

THIS DOCUMENT IS PROVIDED “AS IS”. ARM PROVIDES NO REPRESENTATIONS AND NO WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, SATISFACTORY QUALITY, NON-INFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE WITH RESPECT TO THE DOCUMENT. For the avoidance of doubt, ARM makes no representation with respect to, and has undertaken no analysis to identify or understand the scope and content of, third party patents, copyrights, trade secrets, or other rights.

This document may include technical inaccuracies or typographical errors.


This document consists solely of commercial items. You shall be responsible for ensuring that any use, duplication or disclosure of this document complies fully with any relevant export laws and regulations to assure that this document or any portion thereof is not exported, directly or indirectly, in violation of such export laws. Use of the word “partner” in reference to ARM’s customers is not intended to create or refer to any partnership relationship with any other company. ARM may make changes to this document at any time and without notice.

If any of the provisions contained in these terms conflict with any of the provisions of any signed written agreement covering this document with ARM, then the signed written agreement prevails over and supersedes the conflicting provisions of these terms. This document may be translated into other languages for convenience, and you agree that if there is any conflict between the English version of this document and any translation, the terms of the English version of the Agreement shall prevail.

Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM Limited or its affiliates in the EU and/or elsewhere. All rights reserved. Other brands and names mentioned in this document may be the trademarks of their respective owners. Please follow ARM’s trademark usage guidelines at

Copyright © 2014, 2015, 2017, ARM Limited or its affiliates. All rights reserved.

ARM Limited. Company 02557590 registered in England.

110 Fulbourn Road, Cambridge, England CB1 9NJ.


Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Unrestricted Access is an ARM internal classification.

Product Status

The information in this document is Final, that is for a developed product.

Web Address

Non-ConfidentialPDF file icon PDF versionARM 100052_0001_00_en
Copyright © 2014, 2015, 2017 ARM Limited or its affiliates. All rights reserved.