3.4 Migrating architecture and processor names for command-line options

There are minor differences between the architecture and processor names that Arm® Compiler 6 recognizes, and the names that Arm Compiler 5 recognizes. Within Arm Compiler 6, there are differences in the architecture and processor names that armclang recognizes and the names that armasm, armlink, and fromelf recognize. This topic shows the differences in the architecture and processor names for the different tools in Arm Compiler 5 and Arm Compiler 6.

The tables show the documented --cpu options in Arm Compiler 5 and their corresponding options for migrating your Arm Compiler 5 command-line options to Arm Compiler 6.

Note:

The tables assume the default floating-point unit derived from the --cpu option in Arm Compiler 5. However, in Arm Compiler 6, armclang selects different defaults for floating-point unit (VFP) and Advanced SIMD. Therefore, the tables also show how to use the armclang -mfloat-abi and -mfpu options to be compatible with the default floating-point unit in Arm Compiler 5. The tables do not provide an exhaustive list.

Table 3-2 Architecture selection in Arm Compiler 5 and Arm Compiler 6

armcc, armlink, armasm, and fromelf option in Arm Compiler 5 armclang option in Arm Compiler 6 armlink, armasm, and fromelf option in Arm Compiler 6 Architecture description
--cpu=4 Not supported Not supported Armv4
--cpu=4T Not supported Not supported Armv4T
--cpu=5T Not supported Not supported Armv5T
--cpu=5TE Not supported Not supported Armv5TE
--cpu=5TEJ Not supported Not supported Armv5TEJ
--cpu=6 Not supported Not supported Generic Armv6
--cpu=6-K Not supported Not supported Armv6-K
--cpu=6-Z Not supported Not supported Armv6-Z
--cpu=6T2 Not supported Not supported Armv6T2
--cpu=6-M --target=arm-arm-none-eabi -march=armv6-m --cpu=6-M Armv6‑M
--cpu=6S-M --target=arm-arm-none-eabi -march=armv6s-m --cpu=6S-M Armv6S-M

--cpu=7-A

--cpu=7-A.security

--target=arm-arm-none-eabi -march=armv7-a -mfloat-abi=soft --cpu=7-A.security

Armv7‑A without VFP and Advanced SIMD.

In Arm Compiler 5, security extension is not enabled with --cpu=7-A but is enabled with --cpu=7-A.security. In Arm Compiler 6, armclang always enables the Armv7‑A TrustZone security extension with -march=armv7-a. However, armclang does not generate an SMC instruction unless you specify it with an intrinsic or inline assembly.

--cpu=7-R --target=arm-arm-none-eabi -march=armv7-r -mfloat-abi=soft --cpu=7-R Armv7‑R without VFP and Advanced SIMD
--cpu=7-M --target=arm-arm-none-eabi -march=armv7-m --cpu=7-M Armv7‑M
--cpu=7E-M --target=arm-arm-none-eabi -march=armv7e-m -mfloat-abi=soft --cpu=7E-M Armv7E-M

Table 3-3 Processor selection in Arm Compiler 5 and Arm Compiler 6

armcc, armlink, armasm, and fromelf option in Arm Compiler 5 armclang option in Arm Compiler 6 armlink, armasm, and fromelf option in Arm Compiler 6 Description
--cpu=Cortex-A5 --target=arm-arm-none-eabi -mcpu=cortex-a5 -mfloat-abi=soft --cpu=Cortex-A5.no_neon.no_vfp Cortex®‑A5 without Advanced SIMD and VFP
--cpu=Cortex-A5.neon --target=arm-arm-none-eabi -mcpu=cortex-a5 -mfloat-abi=hard --cpu=Cortex-A5 Cortex‑A5 with Advanced SIMD and VFP
--cpu=Cortex-A5.vfp --target=arm-arm-none-eabi -mcpu=cortex-a5 -mfloat-abi=hard -mfpu=vfpv4-d16 --cpu=Cortex-A5.no_neon Cortex‑A5 with VFP, without Advanced SIMD
--cpu=Cortex-A7 --target=arm-arm-none-eabi -mcpu=cortex-a7 -mfloat-abi=hard --cpu=Cortex-A7 Cortex‑A7 with Advanced SIMD and VFP
--cpu=Cortex-A7.no_neon.no_vfp --target=arm-arm-none-eabi -mcpu=cortex-a7 -mfloat-abi=soft --cpu=Cortex-A7.no_neon.no_vfp Cortex‑A7 without Advanced SIMD and VFP
--cpu=Cortex-A7.no_neon --target=arm-arm-none-eabi -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=vfpv4-d16 --cpu=Cortex-A7.no_neon Cortex‑A7 with VFP, without Advanced SIMD
--cpu=Cortex-A8 --target=arm-arm-none-eabi -mcpu=cortex-a8 -mfloat-abi=hard --cpu=Cortex-A8 Cortex‑A8 with VFP and Advanced SIMD
--cpu=Cortex-A8.no_neon --target=arm-arm-none-eabi -mcpu=cortex-a8 -mfloat-abi=soft --cpu=Cortex-A8.no_neon Cortex‑A8 without Advanced SIMD and VFP
--cpu=Cortex-A9 --target=arm-arm-none-eabi -mcpu=cortex-a9 -mfloat-abi=hard --cpu=Cortex-A9 Cortex-A9 with Advanced SIMD and VFP
--cpu=Cortex-A9.no_neon.no_vfp --target=arm-arm-none-eabi -mcpu=cortex-a9 -mfloat-abi=soft --cpu=Cortex-A9.no_neon.no_vfp Cortex‑A9 without Advanced SIMD and VFP
--cpu=Cortex-A9.no_neon --target=arm-arm-none-eabi -mcpu=cortex-a9 -mfloat-abi=hard -mfpu=vfpv3-d16-fp16 --cpu=Cortex-A9.no_neon Cortex‑A9 with VFP but without Advanced SIMD
--cpu=Cortex-A12 --target=arm-arm-none-eabi -mcpu=cortex-a12 -mfloat-abi=hard --cpu=Cortex-A12 Cortex‑A12 with Advanced SIMD and VFP
--cpu=Cortex-A12.no_neon.no_vfp --target=arm-arm-none-eabi -mcpu=cortex-a12 -mfloat-abi=soft --cpu=Cortex-A12.no_neon.no_vfp Cortex‑A12 without Advanced SIMD and VFP
--cpu=Cortex-A15 --target=arm-arm-none-eabi -mcpu=cortex-a15 -mfloat-abi=hard --cpu=Cortex-A15 Cortex‑A15 with Advanced SIMD and VFP
--cpu=Cortex-A15.no_neon --target=arm-arm-none-eabi -mcpu=cortex-a15 -mfloat-abi=hard -mfpu=vfpv4-d16 --cpu=Cortex-A15.no_neon Cortex‑A15 with VFP, without Advanced SIMD
--cpu=Cortex-A15.no_neon.no_vfp --target=arm-arm-none-eabi -mcpu=cortex-a15 -mfloat-abi=soft --cpu=Cortex-A15.no_neon.no_vfp Cortex‑A15 without Advanced SIMD and VFP
--cpu=Cortex-A17 --target=arm-arm-none-eabi -mcpu=cortex-a17 -mfloat-abi=hard --cpu=Cortex-A17 Cortex-A17 with Advanced SIMD and VFP
--cpu=Cortex-A17.no_neon.no_vfp --target=arm-arm-none-eabi -mcpu=cortex-a17 -mfloat-abi=soft --cpu=Cortex-A17.no_neon.no_vfp Cortex‑A17 without Advanced SIMD and VFP
--cpu=Cortex-R4 --target=arm-arm-none-eabi -mcpu=cortex-r4 --cpu=Cortex-R4 Cortex‑R4 without VFP
--cpu=Cortex-R4F --target=arm-arm-none-eabi -mcpu=cortex-r4f -mfloat-abi=hard --cpu=Cortex-R4F Cortex‑R4 with VFP
--cpu=Cortex-R5 --target=arm-arm-none-eabi -mcpu=cortex-r5 -mfloat-abi=soft --cpu=Cortex-R5.no_vfp Cortex‑R5 without VFP
--cpu=Cortex-R5F --target=arm-arm-none-eabi -mcpu=cortex-r5 -mfloat-abi=hard --cpu=Cortex-R5 Cortex‑R5 with double precision VFP
--cpu=Cortex-R5F-rev1.sp --target=arm-arm-none-eabi -mcpu=cortex-r5 -mfloat-abi=hard -mfpu=vfpv3xd --cpu=Cortex-R5.sp Cortex‑R5 with single precision VFP
--cpu=Cortex-R7 --target=arm-arm-none-eabi -mcpu=cortex-r7 -mfloat-abi=hard --cpu=Cortex-R7 Cortex‑R7 with VFP
--cpu=Cortex-R7.no_vfp --target=arm-arm-none-eabi -mcpu=cortex-r7 -mfloat-abi=soft --cpu=Cortex-R7.no_vfp Cortex‑R7 without VFP
--cpu=Cortex-R8 --target=arm-arm-none-eabi -mcpu=cortex-r8 -mfloat-abi=hard --cpu=Cortex-R8 Cortex‑R8 with VFP
--cpu=Cortex-R8.no_vfp --target=arm-arm-none-eabi -mcpu=cortex-r8 -mfloat-abi=soft --cpu=Cortex-R8.no_vfp Cortex‑R8 without VFP
--cpu=Cortex-M0 --target=arm-arm-none-eabi -mcpu=cortex-m0 --cpu=Cortex-M0 Cortex‑M0
--cpu=Cortex-M0plus --target=arm-arm-none-eabi -mcpu=cortex-m0plus --cpu=Cortex-M0plus Cortex‑M0+
--cpu=Cortex-M1 --target=arm-arm-none-eabi -mcpu=cortex-m1 --cpu=Cortex-M1 Cortex‑M1
--cpu=Cortex-M3 --target=arm-arm-none-eabi -mcpu=cortex-m3 --cpu=Cortex-M3 Cortex‑M3
--cpu=Cortex-M4 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfloat-abi=soft --cpu=Cortex-M4.no_fp Cortex‑M4 without VFP
--cpu=Cortex-M4.fp --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfloat-abi=hard --cpu=Cortex-M4 Cortex‑M4 with VFP
--cpu=Cortex-M7 --target=arm-arm-none-eabi -mcpu=cortex-m7 -mfloat-abi=soft --cpu=Cortex-M7.no_fp Cortex‑M7 without VFP
--cpu=Cortex-M7.fp.dp --target=arm-arm-none-eabi -mcpu=cortex-m7 -mfloat-abi=hard --cpu=Cortex-M7 Cortex‑M7 with double precision VFP
--cpu=Cortex-M7.fp.sp --target=arm-arm-none-eabi -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-sp-d16 --cpu=Cortex-M7.fp.sp Cortex‑M7 with single precision VFP

Enabling or disabling architectural features in Arm® Compiler 6

Arm Compiler 6, by default, automatically enables or disables certain architectural features such as the floating-point unit, Advanced SIMD, and Cryptographic extensions depending on the specified architecture or processor. For a list of architectural features, see -mcpu in the armclang Reference Guide. You can override the defaults using other options.

For armclang:

  • For AArch64 targets, you must use either -march or -mcpu to specify the architecture or processor and the required architectural features. You can use +[no]feature with -march or -mcpu to override any architectural feature.
  • For AArch32 targets, you must use either -march or -mcpu to specify the architecture or processor and the required architectural features. You can use -mfloat-abi to override floating-point linkage. You can use -mfpu to override floating-point unit, Advanced SIMD, and Cryptographic extensions. You can use +[no]feature with -march or -mcpu to override certain other architectural features.

For armasm, armlink, and fromelf, you must use the --cpu option to specify the architecture or processor and the required architectural features. You can use --fpu to override the floating-point unit and floating-point linkage. The --cpu option is not mandatory for armlink and fromelf, but is mandatory for armasm.

Note:

  • In Arm Compiler 5, if you use the armcc --fpu=none option, the compiler generates an error if it detects floating-point code. This behavior is different in Arm Compiler 6. If you use the armclang -mfpu=none option, the compiler automatically uses software floating-point libraries if it detects any floating-point code. You cannot use the armlink --fpu=none option to link object files created using armclang.
  • To link object files created using the armclang -mfpu=none option, you must set armlink --fpu to an option that supports software floating-point linkage, for example --fpu=SoftVFP, rather than using --fpu=none.
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