5.16 Data definition directives

Data definition directives allocate memory, define data structures, and set initial contents of memory.

The following table shows how to translate armasm syntax data definition directives to GNU syntax directives:

Note:

This list only contains examples of common data definition assembly directives. It is not exhaustive.

Table 5-6 Data definition directives translation

armasm syntax directive GNU syntax directive Description
DCB .byte Allocate one-byte blocks of memory, and specify the initial contents.
DCW .hword Allocate two-byte blocks of memory, and specify the initial contents.
DCD .word Allocate four-byte blocks of memory, and specify the initial contents.
DCI .inst Allocate a block of memory in the code, and specify the opcode. In A32 code, this is a four-byte block. In T32 code, this can be a two-byte or four-byte block. .inst.n allocates a two-byte block and .inst.w allocates a four-byte block.
DCQ .quad Allocate eight-byte blocks of memory, and specify the initial contents.
SPACE .org

Allocate a zeroed block of memory.

The armasm syntax SPACE directive allocates a zeroed block of memory with the specified size. The GNU assembly .org directive zeroes the memory up to the given address. The address must be greater than the address at which the directive is placed.

The following example shows the armasm syntax and GNU syntax methods of creating a 100-byte zeroed block of memory using these directives:

;  armasm syntax implementation
start_address   SPACE   0x100

// GNU syntax implementation
start_address:
.org    start_address + 0x100

Note:

If label arithmetic is not required, the GNU assembly .space directive can be used instead of the .org directive. However, Arm recommends using the .org directive wherever possible.

The following examples show how to rewrite a vector table in both armasm and GNU syntax.

armasm syntax GNU syntax
Vectors
LDR PC, Reset_Addr
LDR PC, Undefined_Addr
LDR PC, SVC_Addr
LDR PC, Prefetch_Addr
LDR PC, Abort_Addr
B .                       ; Reserved vector
LDR PC, IRQ_Addr
LDR PC, FIQ_Addr

Reset_Addr      DCD     Reset_Handler
Undefined_Addr  DCD     Undefined_Handler
SVC_Addr        DCD     SVC_Handler
Prefetch_Addr   DCD     Prefetch_Handler
Abort_Addr      DCD     Abort_Handler
IRQ_Addr        DCD     IRQ_Handler
FIQ_Addr        DCD     FIQ_Handler
Vectors:
ldr pc, Reset_Addr
ldr pc, Undefined_Addr
ldr pc, SVC_Addr
ldr pc, Prefetch_Addr
ldr pc, Abort_Addr
b .                       // Reserved vector
ldr pc, IRQ_Addr
ldr pc, FIQ_Addr

.balign 4
Reset_Addr:
.word Reset_Handler
Undefined_Addr:
.word Undefined_Handler
SVC_Addr:
.word SVC_Handler
Prefetch_Addr:
.word Prefetch_Handler
Abort_Addr:
.word Abort_Handler
IRQ_Addr:
.word IRQ_Handler
FIQ_Addr:
word FIQ_Handler
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