ARM® Compiler armasm User Guide

Version 6.7


Table of Contents

Preface
About this book
Using this book
Glossary
Typographic conventions
Feedback
Other information
1 Overview of the Assembler
1.1 About the ARM Compiler toolchain assemblers
1.2 Key features of the assembler
1.3 How the assembler works
1.4 Directives that can be omitted in pass 2 of the assembler
1.5 Support level definitions
2 Overview of the ARM Architecture
2.1 About the ARM architecture
2.2 A32 and T32 instruction sets
2.3 A64 instruction set
2.4 Changing between AArch64 and AArch32 states
2.5 Advanced SIMD
2.6 Floating-point hardware
3 Overview of AArch32 state
3.1 Changing between A32 and T32 instruction set states
3.2 Processor modes, and privileged and unprivileged software execution
3.3 Processor modes in ARMv6-M, ARMv7-M, and ARMv8-M
3.4 Registers in AArch32 state
3.5 General-purpose registers in AArch32 state
3.6 Register accesses in AArch32 state
3.7 Predeclared core register names in AArch32 state
3.8 Predeclared extension register names in AArch32 state
3.9 Program Counter in AArch32 state
3.10 The Q flag in AArch32 state
3.11 Application Program Status Register
3.12 Current Program Status Register in AArch32 state
3.13 Saved Program Status Registers in AArch32 state
3.14 A32 and T32 instruction set overview
3.15 Access to the inline barrel shifter in AArch32 state
4 Overview of AArch64 state
4.1 Registers in AArch64 state
4.2 Exception levels
4.3 Link registers
4.4 Stack Pointer register
4.5 Predeclared core register names in AArch64 state
4.6 Predeclared extension register names in AArch64 state
4.7 Program Counter in AArch64 state
4.8 Conditional execution in AArch64 state
4.9 The Q flag in AArch64 state
4.10 Process State
4.11 Saved Program Status Registers in AArch64 state
4.12 A64 instruction set overview
5 Structure of Assembly Language Modules
5.1 Syntax of source lines in assembly language
5.2 Literals
5.3 ELF sections and the AREA directive
5.4 An example ARM assembly language module
6 Writing A32/T32 Assembly Language
6.1 About the Unified Assembler Language
6.2 Syntax differences between UAL and A64 assembly language
6.3 Register usage in subroutine calls
6.4 Load immediate values
6.5 Load immediate values using MOV and MVN
6.6 Load immediate values using MOV32
6.7 Load immediate values using LDR Rd, =const
6.8 Literal pools
6.9 Load addresses into registers
6.10 Load addresses to a register using ADR
6.11 Load addresses to a register using ADRL
6.12 Load addresses to a register using LDR Rd, =label
6.13 Other ways to load and store registers
6.14 Load and store multiple register instructions
6.15 Load and store multiple register instructions in A32 and T32
6.16 Stack implementation using LDM and STM
6.17 Stack operations for nested subroutines
6.18 Block copy with LDM and STM
6.19 Memory accesses
6.20 The Read-Modify-Write operation
6.21 Optional hash with immediate constants
6.22 Use of macros
6.23 Test-and-branch macro example
6.24 Unsigned integer division macro example
6.25 Instruction and directive relocations
6.26 Symbol versions
6.27 Frame directives
6.28 Exception tables and Unwind tables
7 Condition Codes
7.1 Conditional instructions
7.2 Conditional execution in A32 code
7.3 Conditional execution in T32 code
7.4 Conditional execution in A64 code
7.5 Condition flags
7.6 Updates to the condition flags in A32/T32 code
7.7 Updates to the condition flags in A64 code
7.8 Floating-point instructions that update the condition flags
7.9 Carry flag
7.10 Overflow flag
7.11 Condition code suffixes
7.12 Condition code suffixes and related flags
7.13 Comparison of condition code meanings in integer and floating-point code
7.14 Benefits of using conditional execution in A32 and T32 code
7.15 Example showing the benefits of conditional instructions in A32 and T32 code
7.16 Optimization for execution speed
8 Using armasm
8.1 armasm command-line syntax
8.2 Specify command-line options with an environment variable
8.3 Using stdin to input source code to the assembler
8.4 Built-in variables and constants
8.5 Identifying versions of armasm in source code
8.6 Diagnostic messages
8.7 Interlocks diagnostics
8.8 Automatic IT block generation in T32 code
8.9 T32 branch target alignment
8.10 T32 code size diagnostics
8.11 A32 and T32 instruction portability diagnostics
8.12 T32 instruction width diagnostics
8.13 Two pass assembler diagnostics
8.14 Using the C preprocessor
8.15 Address alignment in A32/T32 code
8.16 Address alignment in A64 code
8.17 Instruction width selection in T32 code
9 Advanced SIMD Programming
9.1 Architecture support for Advanced SIMD
9.2 Extension register bank mapping for Advanced SIMD in AArch32 state
9.3 Extension register bank mapping for Advanced SIMD in AArch64 state
9.4 Views of the Advanced SIMD register bank in AArch32 state
9.5 Views of the Advanced SIMD register bank in AArch64 state
9.6 Differences between A32/T32 and A64 Advanced SIMD instruction syntax
9.7 Load values to Advanced SIMD registers
9.8 Conditional execution of A32/T32 Advanced SIMD instructions
9.9 Floating-point exceptions for Advanced SIMD in A32/T32 instructions
9.10 Advanced SIMD data types in A32/T32 instructions
9.11 Polynomial arithmetic over {0,1}
9.12 Advanced SIMD vectors
9.13 Normal, long, wide, and narrow Advanced SIMD instructions
9.14 Saturating Advanced SIMD instructions
9.15 Advanced SIMD scalars
9.16 Extended notation extension for Advanced SIMD in A32/T32 code
9.17 Advanced SIMD system registers in AArch32 state
9.18 Flush-to-zero mode in Advanced SIMD
9.19 When to use flush-to-zero mode in Advanced SIMD
9.20 The effects of using flush-to-zero mode in Advanced SIMD
9.21 Advanced SIMD operations not affected by flush-to-zero mode
10 Floating-point Programming
10.1 Architecture support for floating-point
10.2 Extension register bank mapping for floating-point in AArch32 state
10.3 Extension register bank mapping in AArch64 state
10.4 Views of the floating-point extension register bank in AArch32 state
10.5 Views of the floating-point extension register bank in AArch64 state
10.6 Differences between A32/T32 and A64 floating-point instruction syntax
10.7 Load values to floating-point registers
10.8 Conditional execution of A32/T32 floating-point instructions
10.9 Floating-point exceptions for floating-point in A32/T32 instructions
10.10 Floating-point data types in A32/T32 instructions
10.11 Extended notation extension for floating-point in A32/T32 code
10.12 Floating-point system registers in AArch32 state
10.13 Flush-to-zero mode in floating-point
10.14 When to use flush-to-zero mode in floating-point
10.15 The effects of using flush-to-zero mode in floating-point
10.16 Floating-point operations not affected by flush-to-zero mode
11 armasm Command-line Options
11.1 --16
11.2 --32
11.3 --apcs=qualifier…qualifier
11.4 --arm
11.5 --arm_only
11.6 --bi
11.7 --bigend
11.8 --brief_diagnostics, --no_brief_diagnostics
11.9 --checkreglist
11.10 --cpreproc
11.11 --cpreproc_opts=option[,option,…]
11.12 --cpu=list
11.13 --cpu=name
11.14 --debug
11.15 --depend=dependfile
11.16 --depend_format=string
11.17 --diag_error=tag[,tag,…]
11.18 --diag_remark=tag[,tag,…]
11.19 --diag_style={arm|ide|gnu}
11.20 --diag_suppress=tag[,tag,…]
11.21 --diag_warning=tag[,tag,…]
11.22 --dllexport_all
11.23 --dwarf2
11.24 --dwarf3
11.25 --errors=errorfile
11.26 --exceptions, --no_exceptions
11.27 --exceptions_unwind, --no_exceptions_unwind
11.28 --execstack, --no_execstack
11.29 --execute_only
11.30 --fpmode=model
11.31 --fpu=list
11.32 --fpu=name
11.33 -g
11.34 --help
11.35 -idir[,dir, …]
11.36 --keep
11.37 --length=n
11.38 --li
11.39 --library_type=lib
11.40 --list=file
11.41 --list=
11.42 --littleend
11.43 -m
11.44 --maxcache=n
11.45 --md
11.46 --no_code_gen
11.47 --no_esc
11.48 --no_hide_all
11.49 --no_regs
11.50 --no_terse
11.51 --no_warn
11.52 -o filename
11.53 --pd
11.54 --predefine "directive"
11.55 --reduce_paths, --no_reduce_paths
11.56 --regnames
11.57 --report-if-not-wysiwyg
11.58 --show_cmdline
11.59 --thumb
11.60 --unaligned_access, --no_unaligned_access
11.61 --unsafe
11.62 --untyped_local_labels
11.63 --version_number
11.64 --via=filename
11.65 --vsn
11.66 --width=n
11.67 --xref
12 Symbols, Literals, Expressions, and Operators
12.1 Symbol naming rules
12.2 Variables
12.3 Numeric constants
12.4 Assembly time substitution of variables
12.5 Register-relative and PC-relative expressions
12.6 Labels
12.7 Labels for PC-relative addresses
12.8 Labels for register-relative addresses
12.9 Labels for absolute addresses
12.10 Numeric local labels
12.11 Syntax of numeric local labels
12.12 String expressions
12.13 String literals
12.14 Numeric expressions
12.15 Syntax of numeric literals
12.16 Syntax of floating-point literals
12.17 Logical expressions
12.18 Logical literals
12.19 Unary operators
12.20 Binary operators
12.21 Multiplicative operators
12.22 String manipulation operators
12.23 Shift operators
12.24 Addition, subtraction, and logical operators
12.25 Relational operators
12.26 Boolean operators
12.27 Operator precedence
12.28 Difference between operator precedence in assembly language and C
13 A32 and T32 Instructions
13.1 A32 and T32 instruction summary
13.2 Instruction width specifiers
13.3 Flexible second operand (Operand2)
13.4 Syntax of Operand2 as a constant
13.5 Syntax of Operand2 as a register with optional shift
13.6 Shift operations
13.7 Saturating instructions
13.8 ADC
13.9 ADD
13.10 ADR (PC-relative)
13.11 ADR (register-relative)
13.12 ADRL pseudo-instruction
13.13 AND
13.14 ASR
13.15 B
13.16 BFC
13.17 BFI
13.18 BIC
13.19 BKPT
13.20 BL
13.21 BLX, BLXNS
13.22 BX, BXNS
13.23 BXJ
13.24 CBZ and CBNZ
13.25 CDP and CDP2
13.26 CLREX
13.27 CLZ
13.28 CMP and CMN
13.29 CPS
13.30 CPY pseudo-instruction
13.31 CRC32
13.32 CRC32C
13.33 DBG
13.34 DCPS1 (T32 instruction)
13.35 DCPS2 (T32 instruction)
13.36 DCPS3 (T32 instruction)
13.37 DMB
13.38 DSB
13.39 EOR
13.40 ERET
13.41 ESB
13.42 HLT
13.43 HVC
13.44 ISB
13.45 IT
13.46 LDA
13.47 LDAEX
13.48 LDC and LDC2
13.49 LDM
13.50 LDR (immediate offset)
13.51 LDR (PC-relative)
13.52 LDR (register offset)
13.53 LDR (register-relative)
13.54 LDR pseudo-instruction
13.55 LDR, unprivileged
13.56 LDREX
13.57 LSL
13.58 LSR
13.59 MCR and MCR2
13.60 MCRR and MCRR2
13.61 MLA
13.62 MLS
13.63 MOV
13.64 MOV32 pseudo-instruction
13.65 MOVT
13.66 MRC and MRC2
13.67 MRRC and MRRC2
13.68 MRS (PSR to general-purpose register)
13.69 MRS (system coprocessor register to ARM register)
13.70 MSR (ARM register to system coprocessor register)
13.71 MSR (general-purpose register to PSR)
13.72 MUL
13.73 MVN
13.74 NEG pseudo-instruction
13.75 NOP
13.76 ORN (T32 only)
13.77 ORR
13.78 PKHBT and PKHTB
13.79 PLD, PLDW, and PLI
13.80 POP
13.81 PUSH
13.82 QADD
13.83 QADD8
13.84 QADD16
13.85 QASX
13.86 QDADD
13.87 QDSUB
13.88 QSAX
13.89 QSUB
13.90 QSUB8
13.91 QSUB16
13.92 RBIT
13.93 REV
13.94 REV16
13.95 REVSH
13.96 RFE
13.97 ROR
13.98 RRX
13.99 RSB
13.100 RSC
13.101 SADD8
13.102 SADD16
13.103 SASX
13.104 SBC
13.105 SBFX
13.106 SDIV
13.107 SEL
13.108 SETEND
13.109 SETPAN
13.110 SEV
13.111 SEVL
13.112 SG
13.113 SHADD8
13.114 SHADD16
13.115 SHASX
13.116 SHSAX
13.117 SHSUB8
13.118 SHSUB16
13.119 SMC
13.120 SMLAxy
13.121 SMLAD
13.122 SMLAL
13.123 SMLALD
13.124 SMLALxy
13.125 SMLAWy
13.126 SMLSD
13.127 SMLSLD
13.128 SMMLA
13.129 SMMLS
13.130 SMMUL
13.131 SMUAD
13.132 SMULxy
13.133 SMULL
13.134 SMULWy
13.135 SMUSD
13.136 SRS
13.137 SSAT
13.138 SSAT16
13.139 SSAX
13.140 SSUB8
13.141 SSUB16
13.142 STC and STC2
13.143 STL
13.144 STLEX
13.145 STM
13.146 STR (immediate offset)
13.147 STR (register offset)
13.148 STR, unprivileged
13.149 STREX
13.150 SUB
13.151 SUBS pc, lr
13.152 SVC
13.153 SWP and SWPB
13.154 SXTAB
13.155 SXTAB16
13.156 SXTAH
13.157 SXTB
13.158 SXTB16
13.159 SXTH
13.160 SYS
13.161 TBB and TBH
13.162 TEQ
13.163 TST
13.164 TT, TTT, TTA, TTAT
13.165 UADD8
13.166 UADD16
13.167 UASX
13.168 UBFX
13.169 UDF
13.170 UDIV
13.171 UHADD8
13.172 UHADD16
13.173 UHASX
13.174 UHSAX
13.175 UHSUB8
13.176 UHSUB16
13.177 UMAAL
13.178 UMLAL
13.179 UMULL
13.180 UND pseudo-instruction
13.181 UQADD8
13.182 UQADD16
13.183 UQASX
13.184 UQSAX
13.185 UQSUB8
13.186 UQSUB16
13.187 USAD8
13.188 USADA8
13.189 USAT
13.190 USAT16
13.191 USAX
13.192 USUB8
13.193 USUB16
13.194 UXTAB
13.195 UXTAB16
13.196 UXTAH
13.197 UXTB
13.198 UXTB16
13.199 UXTH
13.200 WFE
13.201 WFI
13.202 YIELD
14 Advanced SIMD Instructions (32-bit)
14.1 Summary of Advanced SIMD instructions
14.2 Summary of shared Advanced SIMD and floating-point instructions
14.3 Cryptographic instructions
14.4 Interleaving provided by load and store element and structure instructions
14.5 Alignment restrictions in load and store element and structure instructions
14.6 FLDMDBX, FLDMIAX
14.7 FSTMDBX, FSTMIAX
14.8 VABA and VABAL
14.9 VABD and VABDL
14.10 VABS
14.11 VACLE, VACLT, VACGE and VACGT
14.12 VADD
14.13 VADDHN
14.14 VADDL and VADDW
14.15 VAND (immediate)
14.16 VAND (register)
14.17 VBIC (immediate)
14.18 VBIC (register)
14.19 VBIF
14.20 VBIT
14.21 VBSL
14.22 VCADD
14.23 VCEQ (immediate #0)
14.24 VCEQ (register)
14.25 VCGE (immediate #0)
14.26 VCGE (register)
14.27 VCGT (immediate #0)
14.28 VCGT (register)
14.29 VCLE (immediate #0)
14.30 VCLS
14.31 VCLE (register)
14.32 VCLT (immediate #0)
14.33 VCLT (register)
14.34 VCLZ
14.35 VCMLA
14.36 VCMLA (by element)
14.37 VCNT
14.38 VCVT (between fixed-point or integer, and floating-point)
14.39 VCVT (between half-precision and single-precision floating-point)
14.40 VCVT (from floating-point to integer with directed rounding modes)
14.41 VCVTB, VCVTT (between half-precision and double-precision)
14.42 VDUP
14.43 VEOR
14.44 VEXT
14.45 VFMA, VFMS
14.46 VHADD
14.47 VHSUB
14.48 VLDn (single n-element structure to one lane)
14.49 VLDn (single n-element structure to all lanes)
14.50 VLDn (multiple n-element structures)
14.51 VLDM
14.52 VLDR
14.53 VLDR (post-increment and pre-decrement)
14.54 VLDR pseudo-instruction
14.55 VMAX and VMIN
14.56 VMAXNM, VMINNM
14.57 VMLA
14.58 VMLA (by scalar)
14.59 VMLAL (by scalar)
14.60 VMLAL
14.61 VMLS (by scalar)
14.62 VMLS
14.63 VMLSL
14.64 VMLSL (by scalar)
14.65 VMOV (immediate)
14.66 VMOV (register)
14.67 VMOV (between two ARM registers and a 64-bit extension register)
14.68 VMOV (between an ARM register and an Advanced SIMD scalar)
14.69 VMOVL
14.70 VMOVN
14.71 VMOV2
14.72 VMRS
14.73 VMSR
14.74 VMUL
14.75 VMUL (by scalar)
14.76 VMULL
14.77 VMULL (by scalar)
14.78 VMVN (register)
14.79 VMVN (immediate)
14.80 VNEG
14.81 VORN (register)
14.82 VORN (immediate)
14.83 VORR (register)
14.84 VORR (immediate)
14.85 VPADAL
14.86 VPADD
14.87 VPADDL
14.88 VPMAX and VPMIN
14.89 VPOP
14.90 VPUSH
14.91 VQABS
14.92 VQADD
14.93 VQDMLAL and VQDMLSL (by vector or by scalar)
14.94 VQDMULH (by vector or by scalar)
14.95 VQDMULL (by vector or by scalar)
14.96 VQMOVN and VQMOVUN
14.97 VQNEG
14.98 VQRDMULH (by vector or by scalar)
14.99 VQRSHL (by signed variable)
14.100 VQRSHRN and VQRSHRUN (by immediate)
14.101 VQSHL (by signed variable)
14.102 VQSHL and VQSHLU (by immediate)
14.103 VQSHRN and VQSHRUN (by immediate)
14.104 VQSUB
14.105 VRADDHN
14.106 VRECPE
14.107 VRECPS
14.108 VREV16, VREV32, and VREV64
14.109 VRHADD
14.110 VRSHL (by signed variable)
14.111 VRSHR (by immediate)
14.112 VRSHRN (by immediate)
14.113 VRINT
14.114 VRSQRTE
14.115 VRSQRTS
14.116 VRSRA (by immediate)
14.117 VRSUBHN
14.118 VSHL (by immediate)
14.119 VSHL (by signed variable)
14.120 VSHLL (by immediate)
14.121 VSHR (by immediate)
14.122 VSHRN (by immediate)
14.123 VSLI
14.124 VSRA (by immediate)
14.125 VSRI
14.126 VSTM
14.127 VSTn (multiple n-element structures)
14.128 VSTn (single n-element structure to one lane)
14.129 VSTR
14.130 VSTR (post-increment and pre-decrement)
14.131 VSUB
14.132 VSUBHN
14.133 VSUBL and VSUBW
14.134 VSWP
14.135 VTBL and VTBX
14.136 VTRN
14.137 VTST
14.138 VUZP
14.139 VZIP
15 Floating-point Instructions (32-bit)
15.1 Summary of floating-point instructions
15.2 VABS (floating-point)
15.3 VADD (floating-point)
15.4 VCMP, VCMPE
15.5 VCVT (between single-precision and double-precision)
15.6 VCVT (between floating-point and integer)
15.7 VCVT (from floating-point to integer with directed rounding modes)
15.8 VCVT (between floating-point and fixed-point)
15.9 VCVTB, VCVTT (half-precision extension)
15.10 VCVTB, VCVTT (between half-precision and double-precision)
15.11 VDIV
15.12 VFMA, VFMS, VFNMA, VFNMS (floating-point)
15.13 VJCVT
15.14 VLDM (floating-point)
15.15 VLDR (floating-point)
15.16 VLDR (post-increment and pre-decrement, floating-point)
15.17 VLDR pseudo-instruction (floating-point)
15.18 VLLDM
15.19 VLSTM
15.20 VMAXNM, VMINNM (floating-point)
15.21 VMLA (floating-point)
15.22 VMLS (floating-point)
15.23 VMOV (floating-point)
15.24 VMOV (between one ARM register and single precision floating-point register)
15.25 VMOV (between two ARM registers and one or two extension registers)
15.26 VMOV (between an ARM register and half a double precision floating-point register)
15.27 VMRS (floating-point)
15.28 VMSR (floating-point)
15.29 VMUL (floating-point)
15.30 VNEG (floating-point)
15.31 VNMLA (floating-point)
15.32 VNMLS (floating-point)
15.33 VNMUL (floating-point)
15.34 VPOP (floating-point)
15.35 VPUSH (floating-point)
15.36 VRINT (floating-point)
15.37 VSEL
15.38 VSQRT
15.39 VSTM (floating-point)
15.40 VSTR (floating-point)
15.41 VSTR (post-increment and pre-decrement, floating-point)
15.42 VSUB (floating-point)
16 A64 General Instructions
16.1 A64 instructions in alphabetical order
16.2 Register restrictions for A64 instructions
16.3 ADC
16.4 ADCS
16.5 ADD (extended register)
16.6 ADD (immediate)
16.7 ADD (shifted register)
16.8 ADDS (extended register)
16.9 ADDS (immediate)
16.10 ADDS (shifted register)
16.11 ADR
16.12 ADRL pseudo-instruction
16.13 ADRP
16.14 AND (immediate)
16.15 AND (shifted register)
16.16 ANDS (immediate)
16.17 ANDS (shifted register)
16.18 ASR (register)
16.19 ASR (immediate)
16.20 ASRV
16.21 AT
16.22 AUTDA, AUTDZA
16.23 AUTDB, AUTDZB
16.24 AUTIA, AUTIZA, AUTIA1716, AUTIASP, AUTIAZ
16.25 AUTIB, AUTIZB, AUTIB1716, AUTIBSP, AUTIBZ
16.26 B.cond
16.27 B
16.28 BFC
16.29 BFI
16.30 BFM
16.31 BFXIL
16.32 BIC (shifted register)
16.33 BICS (shifted register)
16.34 BL
16.35 BLR
16.36 BLRAA, BLRAAZ, BLRAB, BLRABZ
16.37 BR
16.38 BRAA, BRAAZ, BRAB, BRABZ
16.39 BRK
16.40 CBNZ
16.41 CBZ
16.42 CCMN (immediate)
16.43 CCMN (register)
16.44 CCMP (immediate)
16.45 CCMP (register)
16.46 CINC
16.47 CINV
16.48 CLREX
16.49 CLS
16.50 CLZ
16.51 CMN (extended register)
16.52 CMN (immediate)
16.53 CMN (shifted register)
16.54 CMP (extended register)
16.55 CMP (immediate)
16.56 CMP (shifted register)
16.57 CNEG
16.58 CRC32B, CRC32H, CRC32W, CRC32X
16.59 CRC32CB, CRC32CH, CRC32CW, CRC32CX
16.60 CSEL
16.61 CSET
16.62 CSETM
16.63 CSINC
16.64 CSINV
16.65 CSNEG
16.66 DC
16.67 DCPS1
16.68 DCPS2
16.69 DCPS3
16.70 DMB
16.71 DRPS
16.72 DSB
16.73 EON (shifted register)
16.74 EOR (immediate)
16.75 EOR (shifted register)
16.76 ERET
16.77 ERETAA, ERETAB
16.78 ESB
16.79 EXTR
16.80 HINT
16.81 HLT
16.82 HVC
16.83 IC
16.84 ISB
16.85 LSL (register)
16.86 LSL (immediate)
16.87 LSLV
16.88 LSR (register)
16.89 LSR (immediate)
16.90 LSRV
16.91 MADD
16.92 MNEG
16.93 MOV (to or from SP)
16.94 MOV (inverted wide immediate)
16.95 MOV (wide immediate)
16.96 MOV (bitmask immediate)
16.97 MOV (register)
16.98 MOVK
16.99 MOVL pseudo-instruction
16.100 MOVN
16.101 MOVZ
16.102 MRS
16.103 MSR (immediate)
16.104 MSR (register)
16.105 MSUB
16.106 MUL
16.107 MVN
16.108 NEG (shifted register)
16.109 NEGS
16.110 NGC
16.111 NGCS
16.112 NOP
16.113 ORN (shifted register)
16.114 ORR (immediate)
16.115 ORR (shifted register)
16.116 PACDA, PACDZA
16.117 PACDB, PACDZB
16.118 PACGA
16.119 PACIA, PACIZA, PACIA1716, PACIASP, PACIAZ
16.120 PACIB, PACIZB, PACIB1716, PACIBSP, PACIBZ
16.121 PSB
16.122 RBIT
16.123 RET
16.124 RETAA, RETAB
16.125 REV16
16.126 REV32
16.127 REV64
16.128 REV
16.129 ROR (immediate)
16.130 ROR (register)
16.131 RORV
16.132 SBC
16.133 SBCS
16.134 SBFIZ
16.135 SBFM
16.136 SBFX
16.137 SDIV
16.138 SEV
16.139 SEVL
16.140 SMADDL
16.141 SMC
16.142 SMNEGL
16.143 SMSUBL
16.144 SMULH
16.145 SMULL
16.146 SUB (extended register)
16.147 SUB (immediate)
16.148 SUB (shifted register)
16.149 SUBS (extended register)
16.150 SUBS (immediate)
16.151 SUBS (shifted register)
16.152 SVC
16.153 SXTB
16.154 SXTH
16.155 SXTW
16.156 SYS
16.157 SYSL
16.158 TBNZ
16.159 TBZ
16.160 TLBI
16.161 TST (immediate)
16.162 TST (shifted register)
16.163 UBFIZ
16.164 UBFM
16.165 UBFX
16.166 UDIV
16.167 UMADDL
16.168 UMNEGL
16.169 UMSUBL
16.170 UMULH
16.171 UMULL
16.172 UXTB
16.173 UXTH
16.174 WFE
16.175 WFI
16.176 XPACD, XPACI, XPACLRI
16.177 YIELD
17 A64 Data Transfer Instructions
17.1 A64 data transfer instructions in alphabetical order
17.2 CASA, CASAL, CAS, CASL, CASAL, CAS, CASL
17.3 CASAB, CASALB, CASB, CASLB
17.4 CASAH, CASALH, CASH, CASLH
17.5 CASPA, CASPAL, CASP, CASPL, CASPAL, CASP, CASPL
17.6 LDADDA, LDADDAL, LDADD, LDADDL, LDADDAL, LDADD, LDADDL
17.7 LDADDAB, LDADDALB, LDADDB, LDADDLB
17.8 LDADDAH, LDADDALH, LDADDH, LDADDLH
17.9 LDAPR
17.10 LDAPRB
17.11 LDAPRH
17.12 LDAR
17.13 LDARB
17.14 LDARH
17.15 LDAXP
17.16 LDAXR
17.17 LDAXRB
17.18 LDAXRH
17.19 LDCLRA, LDCLRAL, LDCLR, LDCLRL, LDCLRAL, LDCLR, LDCLRL
17.20 LDCLRAB, LDCLRALB, LDCLRB, LDCLRLB
17.21 LDCLRAH, LDCLRALH, LDCLRH, LDCLRLH
17.22 LDEORA, LDEORAL, LDEOR, LDEORL, LDEORAL, LDEOR, LDEORL
17.23 LDEORAB, LDEORALB, LDEORB, LDEORLB
17.24 LDEORAH, LDEORALH, LDEORH, LDEORLH
17.25 LDLAR
17.26 LDLARB
17.27 LDLARH
17.28 LDNP
17.29 LDP
17.30 LDPSW
17.31 LDR (immediate)
17.32 LDR (literal)
17.33 LDR pseudo-instruction
17.34 LDR (register)
17.35 LDRAA, LDRAB, LDRAB
17.36 LDRB (immediate)
17.37 LDRB (register)
17.38 LDRH (immediate)
17.39 LDRH (register)
17.40 LDRSB (immediate)
17.41 LDRSB (register)
17.42 LDRSH (immediate)
17.43 LDRSH (register)
17.44 LDRSW (immediate)
17.45 LDRSW (literal)
17.46 LDRSW (register)
17.47 LDSETA, LDSETAL, LDSET, LDSETL, LDSETAL, LDSET, LDSETL
17.48 LDSETAB, LDSETALB, LDSETB, LDSETLB
17.49 LDSETAH, LDSETALH, LDSETH, LDSETLH
17.50 LDSMAXA, LDSMAXAL, LDSMAX, LDSMAXL, LDSMAXAL, LDSMAX, LDSMAXL
17.51 LDSMAXAB, LDSMAXALB, LDSMAXB, LDSMAXLB
17.52 LDSMAXAH, LDSMAXALH, LDSMAXH, LDSMAXLH
17.53 LDSMINA, LDSMINAL, LDSMIN, LDSMINL, LDSMINAL, LDSMIN, LDSMINL
17.54 LDSMINAB, LDSMINALB, LDSMINB, LDSMINLB
17.55 LDSMINAH, LDSMINALH, LDSMINH, LDSMINLH
17.56 LDTR
17.57 LDTRB
17.58 LDTRH
17.59 LDTRSB
17.60 LDTRSH
17.61 LDTRSW
17.62 LDUMAXA, LDUMAXAL, LDUMAX, LDUMAXL, LDUMAXAL, LDUMAX, LDUMAXL
17.63 LDUMAXAB, LDUMAXALB, LDUMAXB, LDUMAXLB
17.64 LDUMAXAH, LDUMAXALH, LDUMAXH, LDUMAXLH
17.65 LDUMINA, LDUMINAL, LDUMIN, LDUMINL, LDUMINAL, LDUMIN, LDUMINL
17.66 LDUMINAB, LDUMINALB, LDUMINB, LDUMINLB
17.67 LDUMINAH, LDUMINALH, LDUMINH, LDUMINLH
17.68 LDUR
17.69 LDURB
17.70 LDURH
17.71 LDURSB
17.72 LDURSH
17.73 LDURSW
17.74 LDXP
17.75 LDXR
17.76 LDXRB
17.77 LDXRH
17.78 PRFM (immediate)
17.79 PRFM (literal)
17.80 PRFM (register)
17.81 PRFUM (unscaled offset)
17.82 STADD, STADDL, STADDL
17.83 STADDB, STADDLB
17.84 STADDH, STADDLH
17.85 STCLR, STCLRL, STCLRL
17.86 STCLRB, STCLRLB
17.87 STCLRH, STCLRLH
17.88 STEOR, STEORL, STEORL
17.89 STEORB, STEORLB
17.90 STEORH, STEORLH
17.91 STLLR
17.92 STLLRB
17.93 STLLRH
17.94 STLR
17.95 STLRB
17.96 STLRH
17.97 STLXP
17.98 STLXR
17.99 STLXRB
17.100 STLXRH
17.101 STNP
17.102 STP
17.103 STR (immediate)
17.104 STR (register)
17.105 STRB (immediate)
17.106 STRB (register)
17.107 STRH (immediate)
17.108 STRH (register)
17.109 STSET, STSETL, STSETL
17.110 STSETB, STSETLB
17.111 STSETH, STSETLH
17.112 STSMAX, STSMAXL, STSMAXL
17.113 STSMAXB, STSMAXLB
17.114 STSMAXH, STSMAXLH
17.115 STSMIN, STSMINL, STSMINL
17.116 STSMINB, STSMINLB
17.117 STSMINH, STSMINLH
17.118 STTR
17.119 STTRB
17.120 STTRH
17.121 STUMAX, STUMAXL, STUMAXL
17.122 STUMAXB, STUMAXLB
17.123 STUMAXH, STUMAXLH
17.124 STUMIN, STUMINL, STUMINL
17.125 STUMINB, STUMINLB
17.126 STUMINH, STUMINLH
17.127 STUR
17.128 STURB
17.129 STURH
17.130 STXP
17.131 STXR
17.132 STXRB
17.133 STXRH
17.134 SWPA, SWPAL, SWP, SWPL, SWPAL, SWP, SWPL
17.135 SWPAB, SWPALB, SWPB, SWPLB
17.136 SWPAH, SWPALH, SWPH, SWPLH
18 A64 Floating-point Instructions
18.1 A64 floating-point instructions in alphabetical order
18.2 Register restrictions for A64 instructions
18.3 FABS (scalar)
18.4 FADD (scalar)
18.5 FCCMP
18.6 FCCMPE
18.7 FCMP
18.8 FCMPE
18.9 FCSEL
18.10 FCVT
18.11 FCVTAS (scalar)
18.12 FCVTAU (scalar)
18.13 FCVTMS (scalar)
18.14 FCVTMU (scalar)
18.15 FCVTNS (scalar)
18.16 FCVTNU (scalar)
18.17 FCVTPS (scalar)
18.18 FCVTPU (scalar)
18.19 FCVTZS (scalar, fixed-point)
18.20 FCVTZS (scalar, integer)
18.21 FCVTZU (scalar, fixed-point)
18.22 FCVTZU (scalar, integer)
18.23 FDIV (scalar)
18.24 FJCVTZS
18.25 FMADD
18.26 FMAX (scalar)
18.27 FMAXNM (scalar)
18.28 FMIN (scalar)
18.29 FMINNM (scalar)
18.30 FMOV (register)
18.31 FMOV (general)
18.32 FMOV (scalar, immediate)
18.33 FMSUB
18.34 FMUL (scalar)
18.35 FNEG (scalar)
18.36 FNMADD
18.37 FNMSUB
18.38 FNMUL (scalar)
18.39 FRINTA (scalar)
18.40 FRINTI (scalar)
18.41 FRINTM (scalar)
18.42 FRINTN (scalar)
18.43 FRINTP (scalar)
18.44 FRINTX (scalar)
18.45 FRINTZ (scalar)
18.46 FSQRT (scalar)
18.47 FSUB (scalar)
18.48 LDNP (SIMD and FP)
18.49 LDP (SIMD and FP)
18.50 LDR (immediate, SIMD and FP)
18.51 LDR (literal, SIMD and FP)
18.52 LDR (register, SIMD and FP)
18.53 LDUR (SIMD and FP)
18.54 SCVTF (scalar, fixed-point)
18.55 SCVTF (scalar, integer)
18.56 STNP (SIMD and FP)
18.57 STP (SIMD and FP)
18.58 STR (immediate, SIMD and FP)
18.59 STR (register, SIMD and FP)
18.60 STUR (SIMD and FP)
18.61 UCVTF (scalar, fixed-point)
18.62 UCVTF (scalar, integer)
19 A64 SIMD Scalar Instructions
19.1 A64 SIMD scalar instructions in alphabetical order
19.2 ABS (scalar)
19.3 ADD (scalar)
19.4 ADDP (scalar)
19.5 CMEQ (scalar, register)
19.6 CMEQ (scalar, zero)
19.7 CMGE (scalar, register)
19.8 CMGE (scalar, zero)
19.9 CMGT (scalar, register)
19.10 CMGT (scalar, zero)
19.11 CMHI (scalar, register)
19.12 CMHS (scalar, register)
19.13 CMLE (scalar, zero)
19.14 CMLT (scalar, zero)
19.15 CMTST (scalar)
19.16 DUP (scalar, element)
19.17 FABD (scalar)
19.18 FACGE (scalar)
19.19 FACGT (scalar)
19.20 FADDP (scalar)
19.21 FCMEQ (scalar, register)
19.22 FCMEQ (scalar, zero)
19.23 FCMGE (scalar, register)
19.24 FCMGE (scalar, zero)
19.25 FCMGT (scalar, register)
19.26 FCMGT (scalar, zero)
19.27 FCMLA (scalar, by element)
19.28 FCMLE (scalar, zero)
19.29 FCMLT (scalar, zero)
19.30 FCVTAS (scalar)
19.31 FCVTAU (scalar)
19.32 FCVTMS (scalar)
19.33 FCVTMU (scalar)
19.34 FCVTNS (scalar)
19.35 FCVTNU (scalar)
19.36 FCVTPS (scalar)
19.37 FCVTPU (scalar)
19.38 FCVTXN (scalar)
19.39 FCVTZS (scalar, fixed-point)
19.40 FCVTZS (scalar, integer)
19.41 FCVTZU (scalar, fixed-point)
19.42 FCVTZU (scalar, integer)
19.43 FMAXNMP (scalar)
19.44 FMAXP (scalar)
19.45 FMINNMP (scalar)
19.46 FMINP (scalar)
19.47 FMLA (scalar, by element)
19.48 FMLS (scalar, by element)
19.49 FMUL (scalar, by element)
19.50 FMULX (scalar, by element)
19.51 FMULX (scalar)
19.52 FRECPE (scalar)
19.53 FRECPS (scalar)
19.54 FRSQRTE (scalar)
19.55 FRSQRTS (scalar)
19.56 MOV (scalar)
19.57 NEG (scalar)
19.58 SCVTF (scalar, fixed-point)
19.59 SCVTF (scalar, integer)
19.60 SHL (scalar)
19.61 SLI (scalar)
19.62 SQABS (scalar)
19.63 SQADD (scalar)
19.64 SQDMLAL (scalar, by element)
19.65 SQDMLAL (scalar)
19.66 SQDMLSL (scalar, by element)
19.67 SQDMLSL (scalar)
19.68 SQDMULH (scalar, by element)
19.69 SQDMULH (scalar)
19.70 SQDMULL (scalar, by element)
19.71 SQDMULL (scalar)
19.72 SQNEG (scalar)
19.73 SQRDMLAH (scalar, by element)
19.74 SQRDMLAH (scalar)
19.75 SQRDMLSH (scalar, by element)
19.76 SQRDMLSH (scalar)
19.77 SQRDMULH (scalar, by element)
19.78 SQRDMULH (scalar)
19.79 SQRSHL (scalar)
19.80 SQRSHRN (scalar)
19.81 SQRSHRUN (scalar)
19.82 SQSHL (scalar, immediate)
19.83 SQSHL (scalar, register)
19.84 SQSHLU (scalar)
19.85 SQSHRN (scalar)
19.86 SQSHRUN (scalar)
19.87 SQSUB (scalar)
19.88 SQXTN (scalar)
19.89 SQXTUN (scalar)
19.90 SRI (scalar)
19.91 SRSHL (scalar)
19.92 SRSHR (scalar)
19.93 SRSRA (scalar)
19.94 SSHL (scalar)
19.95 SSHR (scalar)
19.96 SSRA (scalar)
19.97 SUB (scalar)
19.98 SUQADD (scalar)
19.99 UCVTF (scalar, fixed-point)
19.100 UCVTF (scalar, integer)
19.101 UQADD (scalar)
19.102 UQRSHL (scalar)
19.103 UQRSHRN (scalar)
19.104 UQSHL (scalar, immediate)
19.105 UQSHL (scalar, register)
19.106 UQSHRN (scalar)
19.107 UQSUB (scalar)
19.108 UQXTN (scalar)
19.109 URSHL (scalar)
19.110 URSHR (scalar)
19.111 URSRA (scalar)
19.112 USHL (scalar)
19.113 USHR (scalar)
19.114 USQADD (scalar)
19.115 USRA (scalar)
20 A64 SIMD Vector Instructions
20.1 A64 SIMD Vector instructions in alphabetical order
20.2 ABS (vector)
20.3 ADD (vector)
20.4 ADDHN, ADDHN2 (vector)
20.5 ADDP (vector)
20.6 ADDV (vector)
20.7 AND (vector)
20.8 BIC (vector, immediate)
20.9 BIC (vector, register)
20.10 BIF (vector)
20.11 BIT (vector)
20.12 BSL (vector)
20.13 CLS (vector)
20.14 CLZ (vector)
20.15 CMEQ (vector, register)
20.16 CMEQ (vector, zero)
20.17 CMGE (vector, register)
20.18 CMGE (vector, zero)
20.19 CMGT (vector, register)
20.20 CMGT (vector, zero)
20.21 CMHI (vector, register)
20.22 CMHS (vector, register)
20.23 CMLE (vector, zero)
20.24 CMLT (vector, zero)
20.25 CMTST (vector)
20.26 CNT (vector)
20.27 DUP (vector, element)
20.28 DUP (vector, general)
20.29 EOR (vector)
20.30 EXT (vector)
20.31 FABD (vector)
20.32 FABS (vector)
20.33 FACGE (vector)
20.34 FACGT (vector)
20.35 FADD (vector)
20.36 FADDP (vector)
20.37 FCADD (vector)
20.38 FCMEQ (vector, register)
20.39 FCMEQ (vector, zero)
20.40 FCMGE (vector, register)
20.41 FCMGE (vector, zero)
20.42 FCMGT (vector, register)
20.43 FCMGT (vector, zero)
20.44 FCMLA (vector)
20.45 FCMLE (vector, zero)
20.46 FCMLT (vector, zero)
20.47 FCVTAS (vector)
20.48 FCVTAU (vector)
20.49 FCVTL, FCVTL2 (vector)
20.50 FCVTMS (vector)
20.51 FCVTMU (vector)
20.52 FCVTN, FCVTN2 (vector)
20.53 FCVTNS (vector)
20.54 FCVTNU (vector)
20.55 FCVTPS (vector)
20.56 FCVTPU (vector)
20.57 FCVTXN, FCVTXN2 (vector)
20.58 FCVTZS (vector, fixed-point)
20.59 FCVTZS (vector, integer)
20.60 FCVTZU (vector, fixed-point)
20.61 FCVTZU (vector, integer)
20.62 FDIV (vector)
20.63 FMAX (vector)
20.64 FMAXNM (vector)
20.65 FMAXNMP (vector)
20.66 FMAXNMV (vector)
20.67 FMAXP (vector)
20.68 FMAXV (vector)
20.69 FMIN (vector)
20.70 FMINNM (vector)
20.71 FMINNMP (vector)
20.72 FMINNMV (vector)
20.73 FMINP (vector)
20.74 FMINV (vector)
20.75 FMLA (vector, by element)
20.76 FMLA (vector)
20.77 FMLS (vector, by element)
20.78 FMLS (vector)
20.79 FMOV (vector, immediate)
20.80 FMUL (vector, by element)
20.81 FMUL (vector)
20.82 FMULX (vector, by element)
20.83 FMULX (vector)
20.84 FNEG (vector)
20.85 FRECPE (vector)
20.86 FRECPS (vector)
20.87 FRECPX (vector)
20.88 FRINTA (vector)
20.89 FRINTI (vector)
20.90 FRINTM (vector)
20.91 FRINTN (vector)
20.92 FRINTP (vector)
20.93 FRINTX (vector)
20.94 FRINTZ (vector)
20.95 FRSQRTE (vector)
20.96 FRSQRTS (vector)
20.97 FSQRT (vector)
20.98 FSUB (vector)
20.99 INS (vector, element)
20.100 INS (vector, general)
20.101 LD1 (vector, multiple structures)
20.102 LD1 (vector, single structure)
20.103 LD1R (vector)
20.104 LD2 (vector, multiple structures)
20.105 LD2 (vector, single structure)
20.106 LD2R (vector)
20.107 LD3 (vector, multiple structures)
20.108 LD3 (vector, single structure)
20.109 LD3R (vector)
20.110 LD4 (vector, multiple structures)
20.111 LD4 (vector, single structure)
20.112 LD4R (vector)
20.113 MLA (vector, by element)
20.114 MLA (vector)
20.115 MLS (vector, by element)
20.116 MLS (vector)
20.117 MOV (vector, element)
20.118 MOV (vector, from general)
20.119 MOV (vector)
20.120 MOV (vector, to general)
20.121 MOVI (vector)
20.122 MUL (vector, by element)
20.123 MUL (vector)
20.124 MVN (vector)
20.125 MVNI (vector)
20.126 NEG (vector)
20.127 NOT (vector)
20.128 ORN (vector)
20.129 ORR (vector, immediate)
20.130 ORR (vector, register)
20.131 PMUL (vector)
20.132 PMULL, PMULL2 (vector)
20.133 RADDHN, RADDHN2 (vector)
20.134 RBIT (vector)
20.135 REV16 (vector)
20.136 REV32 (vector)
20.137 REV64 (vector)
20.138 RSHRN, RSHRN2 (vector)
20.139 RSUBHN, RSUBHN2 (vector)
20.140 SABA (vector)
20.141 SABAL, SABAL2 (vector)
20.142 SABD (vector)
20.143 SABDL, SABDL2 (vector)
20.144 SADALP (vector)
20.145 SADDL, SADDL2 (vector)
20.146 SADDLP (vector)
20.147 SADDLV (vector)
20.148 SADDW, SADDW2 (vector)
20.149 SCVTF (vector, fixed-point)
20.150 SCVTF (vector, integer)
20.151 SHADD (vector)
20.152 SHL (vector)
20.153 SHLL, SHLL2 (vector)
20.154 SHRN, SHRN2 (vector)
20.155 SHSUB (vector)
20.156 SLI (vector)
20.157 SMAX (vector)
20.158 SMAXP (vector)
20.159 SMAXV (vector)
20.160 SMIN (vector)
20.161 SMINP (vector)
20.162 SMINV (vector)
20.163 SMLAL, SMLAL2 (vector, by element)
20.164 SMLAL, SMLAL2 (vector)
20.165 SMLSL, SMLSL2 (vector, by element)
20.166 SMLSL, SMLSL2 (vector)
20.167 SMOV (vector)
20.168 SMULL, SMULL2 (vector, by element)
20.169 SMULL, SMULL2 (vector)
20.170 SQABS (vector)
20.171 SQADD (vector)
20.172 SQDMLAL, SQDMLAL2 (vector, by element)
20.173 SQDMLAL, SQDMLAL2 (vector)
20.174 SQDMLSL, SQDMLSL2 (vector, by element)
20.175 SQDMLSL, SQDMLSL2 (vector)
20.176 SQDMULH (vector, by element)
20.177 SQDMULH (vector)
20.178 SQDMULL, SQDMULL2 (vector, by element)
20.179 SQDMULL, SQDMULL2 (vector)
20.180 SQNEG (vector)
20.181 SQRDMLAH (vector, by element)
20.182 SQRDMLAH (vector)
20.183 SQRDMLSH (vector, by element)
20.184 SQRDMLSH (vector)
20.185 SQRDMULH (vector, by element)
20.186 SQRDMULH (vector)
20.187 SQRSHL (vector)
20.188 SQRSHRN, SQRSHRN2 (vector)
20.189 SQRSHRUN, SQRSHRUN2 (vector)
20.190 SQSHL (vector, immediate)
20.191 SQSHL (vector, register)
20.192 SQSHLU (vector)
20.193 SQSHRN, SQSHRN2 (vector)
20.194 SQSHRUN, SQSHRUN2 (vector)
20.195 SQSUB (vector)
20.196 SQXTN, SQXTN2 (vector)
20.197 SQXTUN, SQXTUN2 (vector)
20.198 SRHADD (vector)
20.199 SRI (vector)
20.200 SRSHL (vector)
20.201 SRSHR (vector)
20.202 SRSRA (vector)
20.203 SSHL (vector)
20.204 SSHLL, SSHLL2 (vector)
20.205 SSHR (vector)
20.206 SSRA (vector)
20.207 SSUBL, SSUBL2 (vector)
20.208 SSUBW, SSUBW2 (vector)
20.209 ST1 (vector, multiple structures)
20.210 ST1 (vector, single structure)
20.211 ST2 (vector, multiple structures)
20.212 ST2 (vector, single structure)
20.213 ST3 (vector, multiple structures)
20.214 ST3 (vector, single structure)
20.215 ST4 (vector, multiple structures)
20.216 ST4 (vector, single structure)
20.217 SUB (vector)
20.218 SUBHN, SUBHN2 (vector)
20.219 SUQADD (vector)
20.220 SXTL, SXTL2 (vector)
20.221 TBL (vector)
20.222 TBX (vector)
20.223 TRN1 (vector)
20.224 TRN2 (vector)
20.225 UABA (vector)
20.226 UABAL, UABAL2 (vector)
20.227 UABD (vector)
20.228 UABDL, UABDL2 (vector)
20.229 UADALP (vector)
20.230 UADDL, UADDL2 (vector)
20.231 UADDLP (vector)
20.232 UADDLV (vector)
20.233 UADDW, UADDW2 (vector)
20.234 UCVTF (vector, fixed-point)
20.235 UCVTF (vector, integer)
20.236 UHADD (vector)
20.237 UHSUB (vector)
20.238 UMAX (vector)
20.239 UMAXP (vector)
20.240 UMAXV (vector)
20.241 UMIN (vector)
20.242 UMINP (vector)
20.243 UMINV (vector)
20.244 UMLAL, UMLAL2 (vector, by element)
20.245 UMLAL, UMLAL2 (vector)
20.246 UMLSL, UMLSL2 (vector, by element)
20.247 UMLSL, UMLSL2 (vector)
20.248 UMOV (vector)
20.249 UMULL, UMULL2 (vector, by element)
20.250 UMULL, UMULL2 (vector)
20.251 UQADD (vector)
20.252 UQRSHL (vector)
20.253 UQRSHRN, UQRSHRN2 (vector)
20.254 UQSHL (vector, immediate)
20.255 UQSHL (vector, register)
20.256 UQSHRN, UQSHRN2 (vector)
20.257 UQSUB (vector)
20.258 UQXTN, UQXTN2 (vector)
20.259 URECPE (vector)
20.260 URHADD (vector)
20.261 URSHL (vector)
20.262 URSHR (vector)
20.263 URSQRTE (vector)
20.264 URSRA (vector)
20.265 USHL (vector)
20.266 USHLL, USHLL2 (vector)
20.267 USHR (vector)
20.268 USQADD (vector)
20.269 USRA (vector)
20.270 USUBL, USUBL2 (vector)
20.271 USUBW, USUBW2 (vector)
20.272 UXTL, UXTL2 (vector)
20.273 UZP1 (vector)
20.274 UZP2 (vector)
20.275 XTN, XTN2 (vector)
20.276 ZIP1 (vector)
20.277 ZIP2 (vector)
21 Directives Reference
21.1 Alphabetical list of directives
21.2 About assembly control directives
21.3 About frame directives
21.4 ALIAS
21.5 ALIGN
21.6 AREA
21.7 ARM or CODE32 directive
21.8 ASSERT
21.9 ATTR
21.10 CN
21.11 CODE16 directive
21.12 COMMON
21.13 CP
21.14 DATA
21.15 DCB
21.16 DCD and DCDU
21.17 DCDO
21.18 DCFD and DCFDU
21.19 DCFS and DCFSU
21.20 DCI
21.21 DCQ and DCQU
21.22 DCW and DCWU
21.23 END
21.24 ENDFUNC or ENDP
21.25 ENTRY
21.26 EQU
21.27 EXPORT or GLOBAL
21.28 EXPORTAS
21.29 FIELD
21.30 FRAME ADDRESS
21.31 FRAME POP
21.32 FRAME PUSH
21.33 FRAME REGISTER
21.34 FRAME RESTORE
21.35 FRAME RETURN ADDRESS
21.36 FRAME SAVE
21.37 FRAME STATE REMEMBER
21.38 FRAME STATE RESTORE
21.39 FRAME UNWIND ON
21.40 FRAME UNWIND OFF
21.41 FUNCTION or PROC
21.42 GBLA, GBLL, and GBLS
21.43 GET or INCLUDE
21.44 IF, ELSE, ENDIF, and ELIF
21.45 IMPORT and EXTERN
21.46 INCBIN
21.47 INFO
21.48 KEEP
21.49 LCLA, LCLL, and LCLS
21.50 LTORG
21.51 MACRO and MEND
21.52 MAP
21.53 MEXIT
21.54 NOFP
21.55 OPT
21.56 QN, DN, and SN
21.57 RELOC
21.58 REQUIRE
21.59 REQUIRE8 and PRESERVE8
21.60 RLIST
21.61 RN
21.62 ROUT
21.63 SETA, SETL, and SETS
21.64 SPACE or FILL
21.65 THUMB directive
21.66 TTL and SUBT
21.67 WHILE and WEND
21.68 WN and XN
22 Via File Syntax
22.1 Overview of via files
22.2 Via file syntax rules

List of Figures

1-1 Integration boundaries in ARM Compiler 6.
3-1 Organization of general-purpose registers and Program Status Registers
9-1 Extension register bank for Advanced SIMD in AArch32 state
9-2 Extension register bank for Advanced SIMD in AArch64 state
10-1 Extension register bank for floating-point in AArch32 state
10-2 Extension register bank for floating-point in AArch64 state
13-1 ASR #3
13-2 LSR #3
13-3 LSL #3
13-4 ROR #3
13-5 RRX
14-1 De-interleaving an array of 3-element structures
14-2 Operation of doubleword VEXT for imm = 3
14-3 Example of operation of VPADAL (in this case for data type S16)
14-4 Example of operation of VPADD (in this case, for data type I16)
14-5 Example of operation of doubleword VPADDL (in this case, for data type S16)
14-6 Operation of quadword VSHL.I64 Qd, Qm, #1
14-7 Operation of quadword VSLI.64 Qd, Qm, #1
14-8 Operation of doubleword VSRI.64 Dd, Dm, #2
14-9 Operation of doubleword VTRN.8
14-10 Operation of doubleword VTRN.32

List of Tables

3-1 ARM processor modes
3-2 Predeclared core registers in AArch32 state
3-3 Predeclared extension registers in AArch32 state
3-4 A32 instruction groups
4-1 Predeclared core registers in AArch64 state
4-2 Predeclared extension registers in AArch64 state
4-3 A64 instruction groups
6-1 Syntax differences between UAL and A64 assembly language
6-2 A32 state immediate values (8-bit)
6-3 A32 state immediate values in MOV instructions
6-4 32-bit T32 immediate values
6-5 32-bit T32 immediate values in MOV instructions
6-6 Stack-oriented suffixes and equivalent addressing mode suffixes
6-7 Suffixes for load and store multiple instructions
7-1 Condition code suffixes
7-2 Condition code suffixes and related flags
7-3 Condition codes
7-4 Conditional branches only
7-5 All instructions conditional
8-1 Built-in variables
8-2 Built-in Boolean constants
8-3 Predefined macros
8-4 armclang equivalent command-line options
9-1 Differences in syntax and mnemonics between A32/T32 and A64 Advanced SIMD instructions
9-2 Advanced SIMD data types
9-3 Advanced SIMD saturation ranges
10-1 Differences in syntax and mnemonics between A32/T32 and A64 floating-point instructions
11-1 Supported ARM architectures
11-2 Severity of diagnostic messages
11-3 Specifying a command-line option and an AREA directive for GNU-stack sections
12-1 Unary operators that return strings
12-2 Unary operators that return numeric or logical values
12-3 Multiplicative operators
12-4 String manipulation operators
12-5 Shift operators
12-6 Addition, subtraction, and logical operators
12-7 Relational operators
12-8 Boolean operators
12-9 Operator precedence in ARM assembly language
12-10 Operator precedence in C
13-1 Summary of instructions
13-2 PC-relative offsets
13-3 Register-relative offsets
13-4 B instruction availability and range
13-5 BL instruction availability and range
13-6 BLX instruction availability and range
13-7 BX instruction availability and range
13-8 BXJ instruction availability and range
13-9 Permitted instructions inside an IT block
13-10 Offsets and architectures, LDR, word, halfword, and byte
13-11 PC-relative offsets
13-12 Options and architectures, LDR (register offsets)
13-13 Register-relative offsets
13-14 Offsets and architectures, LDR (User mode)
13-15 Offsets and architectures, STR, word, halfword, and byte
13-16 Options and architectures, STR (register offsets)
13-17 Offsets and architectures, STR (User mode)
13-18 Range and encoding of expr
14-1 Summary of Advanced SIMD instructions
14-2 Summary of shared Advanced SIMD and floating-point instructions
14-3 Patterns for immediate value in VBIC (immediate)
14-4 Permitted combinations of parameters for VLDn (single n-element structure to one lane)
14-5 Permitted combinations of parameters for VLDn (single n-element structure to all lanes)
14-6 Permitted combinations of parameters for VLDn (multiple n-element structures)
14-7 Available immediate values in VMOV (immediate)
14-8 Available immediate values in VMVN (immediate)
14-9 Patterns for immediate value in VORR (immediate)
14-10 Available immediate ranges in VQRSHRN and VQRSHRUN (by immediate)
14-11 Available immediate ranges in VQSHL and VQSHLU (by immediate)
14-12 Available immediate ranges in VQSHRN and VQSHRUN (by immediate)
14-13 Results for out-of-range inputs in VRECPE
14-14 Results for out-of-range inputs in VRECPS
14-15 Available immediate ranges in VRSHR (by immediate)
14-16 Available immediate ranges in VRSHRN (by immediate)
14-17 Results for out-of-range inputs in VRSQRTE
14-18 Results for out-of-range inputs in VRSQRTS
14-19 Available immediate ranges in VRSRA (by immediate)
14-20 Available immediate ranges in VSHL (by immediate)
14-21 Available immediate ranges in VSHLL (by immediate)
14-22 Available immediate ranges in VSHR (by immediate)
14-23 Available immediate ranges in VSHRN (by immediate)
14-24 Available immediate ranges in VSRA (by immediate)
14-25 Permitted combinations of parameters for VSTn (multiple n-element structures)
14-26 Permitted combinations of parameters for VSTn (single n-element structure to one lane)
14-27 Operation of doubleword VUZP.8
14-28 Operation of quadword VUZP.32
14-29 Operation of doubleword VZIP.8
14-30 Operation of quadword VZIP.32
15-1 Summary of floating-point instructions
16-1 Summary of A64 general instructions
16-2 ADD (64-bit general registers) specifier combinations
16-3 ADDS (64-bit general registers) specifier combinations
16-4 SYS parameter values corresponding to AT operations
16-5 CMN (64-bit general registers) specifier combinations
16-6 CMP (64-bit general registers) specifier combinations
16-7 SYS parameter values corresponding to DC operations
16-8 SYS parameter values corresponding to IC operations
16-9 SUB (64-bit general registers) specifier combinations
16-10 SUBS (64-bit general registers) specifier combinations
16-11 SYS parameter values corresponding to TLBI operations
17-1 Summary of A64 data transfer instructions
18-1 Summary of A64 floating-point instructions
19-1 Summary of A64 SIMD scalar instructions
19-2 DUP (Scalar) specifier combinations
19-3 FCMLA (Scalar) specifier combinations
19-4 FCVTZS (Scalar) specifier combinations
19-5 FCVTZU (Scalar) specifier combinations
19-6 FMLA (Scalar, single-precision and double-precision) specifier combinations
19-7 FMLS (Scalar, single-precision and double-precision) specifier combinations
19-8 FMUL (Scalar, single-precision and double-precision) specifier combinations
19-9 FMULX (Scalar, single-precision and double-precision) specifier combinations
19-10 MOV (Scalar) specifier combinations
19-11 SCVTF (Scalar) specifier combinations
19-12 SQDMLAL (Scalar) specifier combinations
19-13 SQDMLAL (Scalar) specifier combinations
19-14 SQDMLSL (Scalar) specifier combinations
19-15 SQDMLSL (Scalar) specifier combinations
19-16 SQDMULH (Scalar) specifier combinations
19-17 SQDMULL (Scalar) specifier combinations
19-18 SQDMULL (Scalar) specifier combinations
19-19 SQRDMLAH (Scalar) specifier combinations
19-20 SQRDMLSH (Scalar) specifier combinations
19-21 SQRDMULH (Scalar) specifier combinations
19-22 SQRSHRN (Scalar) specifier combinations
19-23 SQRSHRUN (Scalar) specifier combinations
19-24 SQSHL (Scalar) specifier combinations
19-25 SQSHLU (Scalar) specifier combinations
19-26 SQSHRN (Scalar) specifier combinations
19-27 SQSHRUN (Scalar) specifier combinations
19-28 SQXTN (Scalar) specifier combinations
19-29 SQXTUN (Scalar) specifier combinations
19-30 UCVTF (Scalar) specifier combinations
19-31 UQRSHRN (Scalar) specifier combinations
19-32 UQSHL (Scalar) specifier combinations
19-33 UQSHRN (Scalar) specifier combinations
19-34 UQXTN (Scalar) specifier combinations
20-1 Summary of A64 SIMD Vector instructions
20-2 ADDHN, ADDHN2 (Vector) specifier combinations
20-3 ADDV (Vector) specifier combinations
20-4 DUP (Vector) specifier combinations
20-5 DUP (Vector) specifier combinations
20-6 EXT (Vector) specifier combinations
20-7 FCVTL, FCVTL2 (Vector) specifier combinations
20-8 FCVTN, FCVTN2 (Vector) specifier combinations
20-9 FCVTXN{2} (Vector) specifier combinations
20-10 FCVTZS (Vector) specifier combinations
20-11 FCVTZU (Vector) specifier combinations
20-12 FMLA (Vector, single-precision and double-precision) specifier combinations
20-13 FMLS (Vector, single-precision and double-precision) specifier combinations
20-14 FMUL (Vector, single-precision and double-precision) specifier combinations
20-15 FMULX (Vector, single-precision and double-precision) specifier combinations
20-16 INS (Vector) specifier combinations
20-17 INS (Vector) specifier combinations
20-18 LD1 (One register, immediate offset) specifier combinations
20-19 LD1 (Two registers, immediate offset) specifier combinations
20-20 LD1 (Three registers, immediate offset) specifier combinations
20-21 LD1 (Four registers, immediate offset) specifier combinations
20-22 LD1R (Immediate offset) specifier combinations
20-23 LD2R (Immediate offset) specifier combinations
20-24 LD3R (Immediate offset) specifier combinations
20-25 LD4R (Immediate offset) specifier combinations
20-26 MLA (Vector) specifier combinations
20-27 MLS (Vector) specifier combinations
20-28 MOV (Vector) specifier combinations
20-29 MOV (Vector) specifier combinations
20-30 MUL (Vector) specifier combinations
20-31 PMULL, PMULL2 (Vector) specifier combinations
20-32 RADDHN, RADDHN2 (Vector) specifier combinations
20-33 RSHRN, RSHRN2 (Vector) specifier combinations
20-34 RSUBHN, RSUBHN2 (Vector) specifier combinations
20-35 SABAL, SABAL2 (Vector) specifier combinations
20-36 SABDL, SABDL2 (Vector) specifier combinations
20-37 SADALP (Vector) specifier combinations
20-38 SADDL, SADDL2 (Vector) specifier combinations
20-39 SADDLP (Vector) specifier combinations
20-40 SADDLV (Vector) specifier combinations
20-41 SADDW, SADDW2 (Vector) specifier combinations
20-42 SCVTF (Vector) specifier combinations
20-43 SHL (Vector) specifier combinations
20-44 SHLL, SHLL2 (Vector) specifier combinations
20-45 SHRN, SHRN2 (Vector) specifier combinations
20-46 SLI (Vector) specifier combinations
20-47 SMAXV (Vector) specifier combinations
20-48 SMINV (Vector) specifier combinations
20-49 SMLAL, SMLAL2 (Vector) specifier combinations
20-50 SMLAL, SMLAL2 (Vector) specifier combinations
20-51 SMLSL, SMLSL2 (Vector) specifier combinations
20-52 SMLSL, SMLSL2 (Vector) specifier combinations
20-53 SMOV (32-bit) specifier combinations
20-54 SMOV (64-bit) specifier combinations
20-55 SMULL, SMULL2 (Vector) specifier combinations
20-56 SMULL, SMULL2 (Vector) specifier combinations
20-57 SQDMLAL{2} (Vector) specifier combinations
20-58 SQDMLAL{2} (Vector) specifier combinations
20-59 SQDMLSL{2} (Vector) specifier combinations
20-60 SQDMLSL{2} (Vector) specifier combinations
20-61 SQDMULH (Vector) specifier combinations
20-62 SQDMULL{2} (Vector) specifier combinations
20-63 SQDMULL{2} (Vector) specifier combinations
20-64 SQRDMLAH (Vector) specifier combinations
20-65 SQRDMLSH (Vector) specifier combinations
20-66 SQRDMULH (Vector) specifier combinations
20-67 SQRSHRN{2} (Vector) specifier combinations
20-68 SQRSHRUN{2} (Vector) specifier combinations
20-69 SQSHL (Vector) specifier combinations
20-70 SQSHLU (Vector) specifier combinations
20-71 SQSHRN{2} (Vector) specifier combinations
20-72 SQSHRUN{2} (Vector) specifier combinations
20-73 SQXTN{2} (Vector) specifier combinations
20-74 SQXTUN{2} (Vector) specifier combinations
20-75 SRI (Vector) specifier combinations
20-76 SRSHR (Vector) specifier combinations
20-77 SRSRA (Vector) specifier combinations
20-78 SSHLL, SSHLL2 (Vector) specifier combinations
20-79 SSHR (Vector) specifier combinations
20-80 SSRA (Vector) specifier combinations
20-81 SSUBL, SSUBL2 (Vector) specifier combinations
20-82 SSUBW, SSUBW2 (Vector) specifier combinations
20-83 ST1 (One register, immediate offset) specifier combinations
20-84 ST1 (Two registers, immediate offset) specifier combinations
20-85 ST1 (Three registers, immediate offset) specifier combinations
20-86 ST1 (Four registers, immediate offset) specifier combinations
20-87 SUBHN, SUBHN2 (Vector) specifier combinations
20-88 SXTL, SXTL2 (Vector) specifier combinations
20-89 UABAL, UABAL2 (Vector) specifier combinations
20-90 UABDL, UABDL2 (Vector) specifier combinations
20-91 UADALP (Vector) specifier combinations
20-92 UADDL, UADDL2 (Vector) specifier combinations
20-93 UADDLP (Vector) specifier combinations
20-94 UADDLV (Vector) specifier combinations
20-95 UADDW, UADDW2 (Vector) specifier combinations
20-96 UCVTF (Vector) specifier combinations
20-97 UMAXV (Vector) specifier combinations
20-98 UMINV (Vector) specifier combinations
20-99 UMLAL, UMLAL2 (Vector) specifier combinations
20-100 UMLAL, UMLAL2 (Vector) specifier combinations
20-101 UMLSL, UMLSL2 (Vector) specifier combinations
20-102 UMLSL, UMLSL2 (Vector) specifier combinations
20-103 UMOV (32-bit) specifier combinations
20-104 UMULL, UMULL2 (Vector) specifier combinations
20-105 UMULL, UMULL2 (Vector) specifier combinations
20-106 UQRSHRN{2} (Vector) specifier combinations
20-107 UQSHL (Vector) specifier combinations
20-108 UQSHRN{2} (Vector) specifier combinations
20-109 UQXTN{2} (Vector) specifier combinations
20-110 URSHR (Vector) specifier combinations
20-111 URSRA (Vector) specifier combinations
20-112 USHLL, USHLL2 (Vector) specifier combinations
20-113 USHR (Vector) specifier combinations
20-114 USRA (Vector) specifier combinations
20-115 USUBL, USUBL2 (Vector) specifier combinations
20-116 USUBW, USUBW2 (Vector) specifier combinations
20-117 UXTL, UXTL2 (Vector) specifier combinations
20-118 XTN, XTN2 (Vector) specifier combinations
21-1 List of directives
21-2 OPT directive settings

Release Information

Document History
Issue Date Confidentiality Change
A 14 March 2014 Non-Confidential ARM Compiler v6.00 Release
B 15 December 2014 Non-Confidential ARM Compiler v6.01 Release
C 30 June 2015 Non-Confidential ARM Compiler v6.02 Release
D 18 November 2015 Non-Confidential ARM Compiler v6.3 Release
E 24 February 2016 Non-Confidential ARM Compiler v6.4 Release
F 29 June 2016 Non-Confidential ARM Compiler v6.5 Release
G 04 November 2016 Non-Confidential ARM Compiler v6.6 Release
0607-00 05 April 2017 Non-Confidential ARM Compiler v6.7 Release. Document numbering scheme has changed.

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