17.47 LDSETA, LDSETAL, LDSET, LDSETL, LDSETAL, LDSET, LDSETL

Atomic bit set on word or doubleword in memory.

Syntax

LDSETA Ws, Wt, [Xn|SP] ; 32-bit, acquire

LDSETAL Ws, Wt, [Xn|SP] ; 32-bit, acquire and release

LDSET Ws, Wt, [Xn|SP] ; 32-bit, no memory ordering

LDSETL Ws, Wt, [Xn|SP] ; 32-bit, release

LDSETA Xs, Xt, [Xn|SP] ; 64-bit, acquire

LDSETAL Xs, Xt, [Xn|SP] ; 64-bit, acquire and release

LDSET Xs, Xt, [Xn|SP] ; 64-bit, no memory ordering

LDSETL Xs, Xt, [Xn|SP] ; 64-bit, release

Where:

Ws
Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location.
Wt
Is the 32-bit name of the general-purpose register to be loaded.
Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer.
Xs
Is the 64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location.
Xt
Is the 64-bit name of the general-purpose register to be loaded.

Architectures supported

Supported in ARMv8.1 and later.

Usage

Atomic bit set on word or doubleword in memory atomically loads a 32-bit word or 64-bit doubleword from memory, performs a bitwise OR with the value held in a register on it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register.

  • If the destination register is not one of WZR or XZR, LDSETA and LDSETAL load from memory with acquire semantics.
  • LDSETL and LDSETAL store to memory with release semantics.
  • LDSET has no memory ordering requirements.

For more information about memory ordering semantics see Load-Acquire, Store-Release in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

For information about memory accesses see Load/Store addressing modes in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

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