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|Home > Advanced SIMD Instructions (32-bit) > Alignment restrictions in load and store element and structure instructions|
Many of these instructions allow you to specify memory alignment restrictions.
When the alignment is not specified in the instruction, the alignment restriction is controlled by the A bit (SCTLR bit):
If the A bit is 0, there are no alignment restrictions (except for strongly-ordered or device memory, where accesses must be element-aligned).
If the A bit is 1, accesses must be element-aligned.
If an address is not correctly aligned, an alignment fault occurs.