14.42 VDUP

Vector Duplicate.

Syntax

VDUP{cond}.size Qd, Dm[x]

VDUP{cond}.size Dd, Dm[x]

VDUP{cond}.size Qd, Rm

VDUP{cond}.size Dd, Rm

where:

cond

is an optional condition code.

size

must be 8, 16, or 32.

Qd

specifies the destination register for a quadword operation.

Dd

specifies the destination register for a doubleword operation.

Dm[x]

specifies the Advanced SIMD scalar.

Rm

specifies the ARM register. Rm must not be PC.

Operation

VDUP duplicates a scalar into every element of the destination vector. The source can be an Advanced SIMD scalar or an ARM register.

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