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Home > Advanced SIMD Instructions (32-bit) > VQRDMULH (by vector or by scalar) |

Vector Saturating Rounding Doubling Multiply Returning High Half.

`VQRDMULH`

{

}.`cond`

{`datatype`

}, `Qd`

,
`Qn`

`Qm`

`VQRDMULH`

{

}.`cond`

{`datatype`

}, `Dd`

,
`Dn`

`Dm`

`VQRDMULH`

{

}.`cond`

{`datatype`

}, `Qd`

,
`Qn`

[`Dm`

]
`x`

`VQRDMULH`

{

}.`cond`

{`datatype`

}, `Dd`

,
`Dn`

[`Dm`

]
`x`

where:

`cond`

is an optional condition code.

`datatype`

must be either

`S16`

or`S32`

.`Qd`

,`Qn`

are the destination vector and the first operand vector, for a quadword operation.

`Dd`

,`Dn`

are the destination vector and the first operand vector, for a doubleword operation.

`Qm`

or`Dm`

is the vector holding the second operand, for a by vector operation.

`Dm`

[`x`

]is the scalar holding the second operand, for a by scalar operation.

`VQRDMULH`

multiplies corresponding elements in two vectors, doubles the
results, and places the most significant half of the final results in the destination
vector.

The second operand can be a scalar instead of a vector.

If any of the results overflow, they are saturated. The sticky QC flag (FPSCR bit[27]) is set if saturation occurs. Each result is rounded.