17.20 LDCLRAB, LDCLRALB, LDCLRB, LDCLRLB

Atomic bit clear on byte in memory.

Syntax

LDCLRAB Ws, Wt, [Xn|SP] ; Acquire general registers

LDCLRALB Ws, Wt, [Xn|SP] ; Acquire and release general registers

LDCLRB Ws, Wt, [Xn|SP] ; No memory ordering general registers

LDCLRLB Ws, Wt, [Xn|SP] ; Release general registers

Where:

Ws
Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location.
Wt
Is the 32-bit name of the general-purpose register to be loaded.
Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer.

Architectures supported

Supported in ARMv8.1 and later.

Usage

Atomic bit clear on byte in memory atomically loads an 8-bit byte from memory, performs a bitwise AND with the complement of the value held in a register on it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register.

  • If the destination register is not WZR, LDCLRAB and LDCLRALB load from memory with acquire semantics.
  • LDCLRLB and LDCLRALB store to memory with release semantics.
  • LDCLRB has no memory ordering requirements.

For more information about memory ordering semantics see Load-Acquire, Store-Release in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

For information about memory accesses see Load/Store addressing modes in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

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