17.53 LDSMINA, LDSMINAL, LDSMIN, LDSMINL, LDSMINAL, LDSMIN, LDSMINL

Atomic signed minimum on word or doubleword in memory.

Syntax

LDSMINA Ws, Wt, [Xn|SP] ; 32-bit, acquire

LDSMINAL Ws, Wt, [Xn|SP] ; 32-bit, acquire and release

LDSMIN Ws, Wt, [Xn|SP] ; 32-bit, no memory ordering

LDSMINL Ws, Wt, [Xn|SP] ; 32-bit, release

LDSMINA Xs, Xt, [Xn|SP] ; 64-bit, acquire

LDSMINAL Xs, Xt, [Xn|SP] ; 64-bit, acquire and release

LDSMIN Xs, Xt, [Xn|SP] ; 64-bit, no memory ordering

LDSMINL Xs, Xt, [Xn|SP] ; 64-bit, release

Where:

Ws
Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location.
Wt
Is the 32-bit name of the general-purpose register to be loaded.
Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer.
Xs
Is the 64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location.
Xt
Is the 64-bit name of the general-purpose register to be loaded.

Architectures supported

Supported in ARMv8.1 and later.

Usage

Atomic signed minimum on word or doubleword in memory atomically loads a 32-bit word or 64-bit doubleword from memory, compares it against the value held in a register, and stores the smaller value back to memory, treating the values as signed numbers. The value initially loaded from memory is returned in the destination register.

  • If the destination register is not one of WZR or XZR, LDSMINA and LDSMINAL load from memory with acquire semantics.
  • LDSMINL and LDSMINAL store to memory with release semantics.
  • LDSMIN has no memory ordering requirements.

For more information about memory ordering semantics see Load-Acquire, Store-Release in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

For information about memory accesses see Load/Store addressing modes in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

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