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Home > A64 Data Transfer Instructions > STCLRH, STCLRLH |
Atomic bit clear on halfword in memory, without return.
STCLRH
Ws
, [Xn|SP
] ; No memory ordering general registers
STCLRLH
Ws
, [Xn|SP
] ; Release general registers
Where:
Ws
Xn|SP
Supported in ARMv8.1 and later.
Atomic bit clear on halfword in memory, without return, atomically loads a 16-bit halfword from memory, performs a bitwise AND with the complement of the value held in a register on it, and stores the result back to memory.
STCLRH
has no memory ordering semantics.STCLRLH
stores to memory with release semantics, as described in Load-Acquire, Store-Release.For information about memory accesses see Load/Store addressing modes in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.