3.12 Current Program Status Register in AArch32 state

The Current Program Status Register (CPSR) holds the same program status flags as the APSR, and some additional information.

It holds:

  • The APSR flags.
  • The processor mode.
  • The interrupt disable flags.
  • Either:

    • The instruction set state for ARMv8 (A32 or T32).
    • The instruction set state for ARMv7 (ARM or Thumb).
  • The endianness state.
  • The execution state bits for the IT block.

The execution state bits control conditional execution in the IT block.

Only the APSR flags are accessible in all modes. ARM® deprecates using an MSR instruction to change the endianness bit (E) of the CPSR, in any mode. Each exception level can have its own endianness, but mixed endianness within an exception level is deprecated.

The SETEND instruction is deprecated in A32 and T32 and has no equivalent in A64.

The execution state bits for the IT block (IT[1:0]) and the T32 bit (T) can be accessed by MRS only in Debug state.

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