Non-Confidential | PDF version | ARM 100069_0608_00_en | ||

| ||||

Home > A32 and T32 Instructions > A32 and T32 instruction summary |

An overview of the instructions available in the A32 and T32 instruction sets.

**Table 13-1 Summary of instructions**

Mnemonic | Brief description |
---|---|

`ADC` , `ADD` |
Add with Carry, Add |

`ADR` |
Load program or register-relative address (short range) |

`ADRL` pseudo-instruction |
Load program or register-relative address (medium range) |

`AND` |
Logical AND |

`ASR` |
Arithmetic Shift Right |

`B` |
Branch |

`BFC` , `BFI` |
Bit Field Clear and Insert |

`BIC` |
Bit Clear |

`BKPT` |
Software breakpoint |

`BL` |
Branch with Link |

`BLX` , `BLXNS` |
Branch with Link, change instruction set, Branch with Link and Exchange (Non-secure) |

`BX` ,
`BXNS` |
Branch, change instruction set, Branch and Exchange (Non-secure) |

`CBZ` ,
`CBNZ` |
Compare and Branch if {Non}Zero |

`CDP` |
Coprocessor Data Processing operation |

`CDP2` |
Coprocessor Data Processing operation |

`CLREX` |
Clear Exclusive |

`CLZ` |
Count leading zeros |

`CMN` , `CMP` |
Compare Negative, Compare |

`CPS` |
Change Processor State |

`CPY` pseudo-instruction |
Copy |

`CRC32` |
CRC32 |

`CRC32C` |
CRC32C |

`DBG` |
Debug |

`DCPS1` |
Debug switch to exception level 1 |

`DCPS2` |
Debug switch to exception level 2 |

`DCPS3` |
Debug switch to exception level 3 |

`DMB` , `DSB` |
Data Memory Barrier, Data Synchronization Barrier |

`DSB` |
Data Synchronization Barrier |

`EOR` |
Exclusive OR |

`ERET` |
Exception Return |

`ESB` |
Error Synchronization Barrier |

`HLT` |
Halting breakpoint |

`HVC` |
Hypervisor Call |

`ISB` |
Instruction Synchronization Barrier |

`IT` |
If-Then |

`LDAEX` , `LDAEXB` , `LDAEXH` , `LDAEXD` |
Load-Acquire Register Exclusive Word, Byte, Halfword, Doubleword |

`LDC` , `LDC2` |
Load Coprocessor |

`LDM` |
Load Multiple registers |

`LDR` |
Load Register with word |

`LDR` pseudo-instruction |
Load Register pseudo-instruction |

`LDA` , `LDAB` ,
`LDAH` |
Load-Acquire Register Word, Byte, Halfword |

`LDRB` |
Load Register with Byte |

`LDRBT` |
Load Register with Byte, user mode |

`LDRD` |
Load Registers with two words |

`LDREX` , `LDREXB` , `LDREXH` , `LDREXD` |
Load Register Exclusive Word, Byte, Halfword, Doubleword |

`LDRH` |
Load Register with Halfword |

`LDRHT` |
Load Register with Halfword, user mode |

`LDRSB` |
Load Register with Signed Byte |

`LDRSBT` |
Load Register with Signed Byte, user mode |

`LDRSH` |
Load Register with Signed Halfword |

`LDRSHT` |
Load Register with Signed Halfword, user mode |

`LDRT` |
Load Register with word, user mode |

`LSL` , `LSR` |
Logical Shift Left, Logical Shift Right |

`MCR` |
Move from Register to Coprocessor |

`MCRR` |
Move from Registers to Coprocessor |

`MLA` |
Multiply Accumulate |

`MLS` |
Multiply and Subtract |

`MOV` |
Move |

`MOVT` |
Move Top |

`MOV32` pseudo-instruction |
Move 32-bit immediate to register |

`MRC` |
Move from Coprocessor to Register |

`MRRC` |
Move from Coprocessor to Registers |

`MRS` |
Move from PSR to Register |

`MRS` pseudo-instruction |
Move from system Coprocessor to Register |

`MSR` |
Move from Register to PSR |

`MSR` pseudo-instruction |
Move from Register to system Coprocessor |

`MUL` |
Multiply |

`MVN` |
Move Not |

`NEG` pseudo-instruction |
Negate |

`NOP` |
No Operation |

`ORN` |
Logical OR NOT |

`ORR` |
Logical OR |

`PKHBT` , `PKHTB` |
Pack Halfwords |

`PLD` |
Preload Data |

`PLDW` |
Preload Data with intent to Write |

`PLI` |
Preload Instruction |

`PUSH` , `POP` |
PUSH registers to stack, POP registers from stack |

`QADD` , `QDADD` , `QDSUB` , `QSUB` |
Saturating arithmetic |

`QADD8` , `QADD16` , `QASX` , `QSUB8` , `QSUB16` , `QSAX` |
Parallel signed saturating arithmetic |

`RBIT` |
Reverse Bits |

`REV` , `REV16` , `REVSH` |
Reverse byte order |

`RFE` |
Return From Exception |

`ROR` |
Rotate Right Register |

`RRX` |
Rotate Right with Extend |

`RSB` |
Reverse Subtract |

`RSC` |
Reverse Subtract with Carry |

`SADD8` , `SADD16` , `SASX` |
Parallel Signed arithmetic |

`SBC` |
Subtract with Carry |

`SBFX` , `UBFX` |
Signed, Unsigned Bit Field eXtract |

`SDIV` |
Signed Divide |

`SEL` |
Select bytes according to APSR GE flags |

`SETEND` |
Set Endianness for memory accesses |

`SETPAN` |
Set Privileged Access Never |

`SEV` |
Set Event |

`SEVL` |
Set Event Locally |

`SG` |
Secure Gateway |

`SHADD8` , `SHADD16` , `SHASX` , `SHSUB8` , `SHSUB16` , `SHSAX` |
Parallel Signed Halving arithmetic |

`SMC` |
Secure Monitor Call |

`SMLAxy` |
Signed Multiply with Accumulate (32 <= 16 x 16 + 32) |

`SMLAD` |
Dual Signed Multiply Accumulate |

(32 <= 32 + 16 x 16 + 16 x 16) | |

`SMLAL` |
Signed Multiply Accumulate (64 <= 64 + 32 x 32) |

`SMLALxy` |
Signed Multiply Accumulate (64 <= 64 + 16 x 16) |

`SMLALD` |
Dual Signed Multiply Accumulate Long |

(64 <= 64 + 16 x 16 + 16 x 16) | |

`SMLAWy` |
Signed Multiply with Accumulate (32 <= 32 x 16 + 32) |

`SMLSD` |
Dual Signed Multiply Subtract Accumulate |

(32 <= 32 + 16 x 16 – 16 x 16) | |

`SMLSLD` |
Dual Signed Multiply Subtract Accumulate Long |

(64 <= 64 + 16 x 16 – 16 x 16) | |

`SMMLA` |
Signed top word Multiply with Accumulate (32 <= TopWord(32 x 32 + 32)) |

`SMMLS` |
Signed top word Multiply with Subtract (32 <= TopWord(32 - 32 x 32)) |

`SMMUL` |
Signed top word Multiply (32 <= TopWord(32 x 32)) |

`SMUAD` , `SMUSD` |
Dual Signed Multiply, and Add or Subtract products |

`SMULxy` |
Signed Multiply (32 <= 16 x 16) |

`SMULL` |
Signed Multiply (64 <= 32 x 32) |

`SMULWy` |
Signed Multiply (32 <= 32 x 16) |

`SRS` |
Store Return State |

`SSAT` |
Signed Saturate |

`SSAT16` |
Signed Saturate, parallel halfwords |

`SSUB8` , `SSUB16` , `SSAX` |
Parallel Signed arithmetic |

`STC` |
Store Coprocessor |

`STM` |
Store Multiple registers |

`STR` |
Store Register with word |

`STRB` |
Store Register with Byte |

`STRBT` |
Store Register with Byte, user mode |

`STRD` |
Store Registers with two words |

`STREX` , `STREXB` , `STREXH` ,`STREXD` |
Store Register Exclusive Word, Byte, Halfword, Doubleword |

`STRH` |
Store Register with Halfword |

`STRHT` |
Store Register with Halfword, user mode |

`STL` , `STLB` , `STLH` |
Store-Release Word, Byte, Halfword |

`STLEX` , `STLEXB` , `STLEXH` , `STLEXD` |
Store-Release Exclusive Word, Byte, Halfword, Doubleword |

`STRT` |
Store Register with word, user mode |

`SUB` |
Subtract |

`SUBS pc, lr` |
Exception return, no stack |

`SVC` (formerly `SWI` ) |
Supervisor Call |

`SXTAB` ,
`SXTAB16` , `SXTAH` |
Signed extend, with Addition |

`SXTB` ,
`SXTH` |
Signed extend |

`SXTB16` |
Signed extend |

`SYS` |
Execute System coprocessor instruction |

`TBB` , `TBH` |
Table Branch Byte, Halfword |

`TEQ` |
Test Equivalence |

`TST` |
Test |

`TT` , `TTT` , `TTA` , `TTAT` |
Test Target (Alternate Domain, Unprivileged) |

`UADD8` , `UADD16` , `UASX` |
Parallel Unsigned arithmetic |

`UDF` |
Permanently Undefined |

`UDIV` |
Unsigned Divide |

`UHADD8` , `UHADD16` , `UHASX` , `UHSUB8` , `UHSUB16` , `UHSAX` |
Parallel Unsigned Halving arithmetic |

`UMAAL` |
Unsigned Multiply Accumulate Accumulate Long |

(64 <= 32 + 32 + 32 x 32) | |

`UMLAL` , `UMULL` |
Unsigned Multiply Accumulate, Unsigned Multiply |

(64 <= 32 x 32 + 64), (64 <= 32 x 32) | |

`UQADD8` , `UQADD16` , `UQASX` , `UQSUB8` , `UQSUB16` , `UQSAX` |
Parallel Unsigned Saturating arithmetic |

`USAD8` |
Unsigned Sum of Absolute Differences |

`USADA8` |
Accumulate Unsigned Sum of Absolute Differences |

`USAT` |
Unsigned Saturate |

`USAT16` |
Unsigned Saturate, parallel halfwords |

`USUB8` , `USUB16` , `USAX` |
Parallel Unsigned arithmetic |

`UXTAB` ,
`UXTAB16` , `UXTAH` |
Unsigned extend with Addition |

`UXTB` ,
`UXTH` |
Unsigned extend |

`UXTB16` |
Unsigned extend |

`V*` |
See Chapter 14 Advanced SIMD Instructions (32-bit) and Chapter 15 Floating-point Instructions (32-bit) |

`WFE` , `WFI` , `YIELD` |
Wait For Event, Wait For Interrupt, Yield |