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Home > A32 and T32 Instructions > LDR (PC-relative) |
Load register. The address is an offset from the PC.
LDR
{
}{type
}{cond
.W
}
, Rt
label
LDRD
{
}
cond
, Rt
,
Rt2
; Doubleword label
where:
type
can be any one of:
B
SB
LDR
only. Sign extend to 32
bits.)H
SH
LDR
only. Sign extend to 32
bits.)-
cond
.W
Rt
Rt2
label
is a PC-relative expression.
label
must be within a
limited distance of the current instruction.
STR
instruction in A32 code but they are deprecated.The assembler calculates the offset from the PC for you. The assembler
generates an error if
is out of range.label
The following table shows the possible offsets between the label and the current instruction:
You can use the .W
width specifier to
force LDR
to generate a 32-bit instruction in T32 code.
LDR.W
always generates a 32-bit instruction, even if the
target could be reached using a 16-bit LDR
.
For forward references, LDR
without
.W
always generates a 16-bit instruction in T32 code,
even if that results in failure for a target that could be reached using a 32-bit T32
LDR
instruction.
For 32-bit T32 instructions, you must not specify SP or PC for either
or Rt
.Rt2
For A32 instructions:
Rt
must be an even-numbered register.Rt
must not be LR.R12
for Rt
.Rt2
must be R(t
+ 1)
.In A32 code, you can use SP for R
in t
LDR
word
instructions. You can use SP for R
in t
LDR
non-word A32 instructions
but this is deprecated.
In T32 code, you can use SP for R
in t
LDR
word
instructions only. All other uses of SP in these instructions are not permitted in T32
code.
For word loads, Rt can be the PC. A load to the PC causes a branch to the address loaded. In ARMv4, bits[1:0] of the address loaded must be 0b00. In ARMv5T and above, bits[1:0] must not be 0b10, and if bit[0] is 1, execution continues in T32 state, otherwise execution continues in A32 state.
In ARMv7-M, LDRD
(PC-relative) instructions must be on a word-aligned address.
Must be a multiple of 4.
Rt must be in the range R0-R7. There are no byte, halfword, or doubleword 16-bit instructions.