17.28 LDNP

Load Pair of Registers, with non-temporal hint.

Syntax

LDNP Wt1, Wt2, [Xn|SP{, #imm}] ; 32-bit

LDNP Xt1, Xt2, [Xn|SP{, #imm}] ; 64-bit

Where:

Wt1
Is the 32-bit name of the first general-purpose register to be transferred.
Wt2
Is the 32-bit name of the second general-purpose register to be transferred.
imm

Depends on the instruction variant:

32-bit general registers
Is the optional signed immediate byte offset, a multiple of 4 in the range -256 to 252, defaulting to 0.
64-bit general registers
Is the optional signed immediate byte offset, a multiple of 8 in the range -512 to 504, defaulting to 0.
Xt1
Is the 64-bit name of the first general-purpose register to be transferred.
Xt2
Is the 64-bit name of the second general-purpose register to be transferred.
Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer.

Usage

Load Pair of Registers, with non-temporal hint, calculates an address from a base register value and an immediate offset, loads two 32-bit words or two 64-bit doublewords from memory, and writes them to two registers.

For information about memory accesses, see Load/Store addressing modes in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile. For information about Non-temporal pair instructions, see Load/Store Non-temporal pair in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

Note:

For information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile, and particularly LDNP.
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