17.30 LDPSW

Load Pair of Registers Signed Word.

Syntax

LDPSW Xt1, Xt2, [Xn|SP], #imm ; Post-index general registers

LDPSW Xt1, Xt2, [Xn|SP, #imm]! ; Pre-index general registers

LDPSW Xt1, Xt2, [Xn|SP{, #imm}] ; Signed offset general registers

Where:

imm

Depends on the instruction variant:

Post-index and Pre-index general registers
Is the signed immediate byte offset, a multiple of 4 in the range -256 to 252.
Signed offset general registers
Is the optional signed immediate byte offset, a multiple of 4 in the range -256 to 252, defaulting to 0.
Xt1
Is the 64-bit name of the first general-purpose register to be transferred.
Xt2
Is the 64-bit name of the second general-purpose register to be transferred.
Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer.

Usage

Load Pair of Registers Signed Word calculates an address from a base register value and an immediate offset, loads two 32-bit words from memory, sign-extends them, and writes them to two registers. For information about memory accesses, see Load/Store addressing modes in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

Note:

For information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile, and particularly LDPSW.
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