18.52 LDR (register, SIMD and FP)

Load SIMD and FP Register (register offset).

Syntax

LDR <Bt>, [Xn|SP, (Wm|Xm), extend {amount}] ; 8-bit FP/SIMD registers

LDR <Bt>, [Xn|SP, Xm{, LSL amount}] ; 8-bit FP/SIMD registers

LDR Ht, [Xn|SP, (Wm|Xm){, extend {amount}}] ; 16-bit FP/SIMD registers

LDR St, [Xn|SP, (Wm|Xm){, extend {amount}}] ; 32-bit

LDR Dt, [Xn|SP, (Wm|Xm){, extend {amount}}] ; 64-bit

LDR Qt, [Xn|SP, (Wm|Xm){, extend {amount}}] ; 128-bit FP/SIMD registers

Where:

<Bt>
Is the 8-bit name of the SIMD and FP register to be transferred.
Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer.
Wm
When "option<0>" is set to 0, is the 32-bit name of the general-purpose index register.
Xm
When "option<0>" is set to 1, is the 64-bit name of the general-purpose index register.
extend

Is the index extend specifier:

8-bit FP/SIMD registers
Can be one of UXTW, SXTW or SXTX.
16-bit FP/SIMD registers
Can be one of UXTW, LSL, SXTW or SXTX.
amount
Is the index shift amount, it must be.
Ht
Is the 16-bit name of the SIMD and FP register to be transferred.
St
Is the 32-bit name of the SIMD and FP register to be transferred.
Dt
Is the 64-bit name of the SIMD and FP register to be transferred.
Qt
Is the 128-bit name of the SIMD and FP register to be transferred.

Usage

Load SIMD and FP Register (register offset). This instruction loads a SIMD and FP register from memory. The address that is used for the load is calculated from a base register value and an offset register value. The offset can be optionally shifted and extended.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

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