17.99 STLXRB

Store-Release Exclusive Register Byte.

Syntax

STLXRB Ws, Wt, [Xn|SP{,#0}]

Where:

Ws
Is the 32-bit name of the general-purpose register into which the status result of the store exclusive is written. The value returned is.
0
If the operation updates memory.
1
If the operation fails to update memory.
Wt
Is the 32-bit name of the general-purpose register to be transferred.
Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer.

Aborts

If a synchronous Data Abort exception is generated by the execution of this instruction:

  • Memory is not updated.
  • Ws is not updated.

Whether the detection of memory aborts happens before or after the check on the local Exclusive Monitor depends on the implementation. As a result a failure of the local monitor can occur on some implementations even if the memory access would give a memory abort.

Usage

Store-Release Exclusive Register Byte stores a byte from a 32-bit register to memory if the PE has exclusive access to the memory address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed. See Synchronization and semaphores in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile. The memory access is atomic. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For information about memory accesses see Load/Store addressing modes in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

Note:

For information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile, and particularly STLXRB.
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