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Home > A64 SIMD Vector Instructions > FCVTZU (vector, fixed-point) |
Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector).
FCVTZU
Vd
.T
, Vn
.T
, #fbits
Where:
Vd
T
Vn
fbits
Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.
A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
The following table shows the valid specifier combinations:
Table 20-11 FCVTZU (Vector) specifier combinations
T |
fbits |
---|---|
4H | |
8H | |
2S | 1 to 32 |
4S | 1 to 32 |
2D | 1 to 64 |