Non-Confidential | PDF version | ARM 100069_0608_00_en | ||
| ||||
Home > A64 SIMD Vector Instructions > LD1 (vector, multiple structures) |
Load multiple single-element structures to one, two, three, or four registers.
LD1 {
Vt
.T
}, [Xn|SP
] ; One register
LD1 {
Vt
.T
, Vt2
.T
}, [Xn|SP
] ; Two registers
LD1 {
Vt
.T
, Vt2
.T
, Vt3
.T
}, [Xn|SP
] ; Three registers
LD1 {
Vt
.T
, Vt2
.T
, Vt3
.T
, Vt4
.T
}, [Xn|SP
] ; Four registers
LD1 {
Vt
.T
}, [Xn|SP
], imm
; One register, immediate offset, Post-index
LD1 {
Vt
.T
}, [Xn|SP
], Xm
; One register, register offset, Post-index
LD1 {
Vt
.T
, Vt2
.T
}, [Xn|SP
], imm
; Two registers, immediate offset, Post-index
LD1 {
Vt
.T
, Vt2
.T
}, [Xn|SP
], Xm
; Two registers, register offset, Post-index
LD1 {
Vt
.T
, Vt2
.T
, Vt3
.T
}, [Xn|SP
], imm
; Three registers, immediate offset, Post-index
LD1 {
Vt
.T
, Vt2
.T
, Vt3
.T
}, [Xn|SP
], Xm
; Three registers, register offset, Post-index
LD1 {
Vt
.T
, Vt2
.T
, Vt3
.T
, Vt4
.T
}, [Xn|SP
], imm
; Four registers, immediate offset, Post-index
LD1 {
Vt
.T
, Vt2
.T
, Vt3
.T
, Vt4
.T
}, [Xn|SP
], Xm
; Four registers, register offset, Post-index
Where:
Vt
Vt2
Vt3
Vt4
imm
Is the post-index immediate offset:
#8
or #16
.
#16
or #32
.
#24
or #48
.
#32
or #64
.
Xm
T
Xn|SP
Load multiple single-element structures to one, two, three, or four registers. This instruction loads multiple single-element structures from memory and writes the result to one, two, three, or four SIMD and FP registers.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
The following tables show valid specifier combinations:
Table 20-18 LD1 (One register, immediate offset) specifier combinations
T |
imm |
---|---|
8B | #8 |
16B | #16 |
4H | #8 |
8H | #16 |
2S | #8 |
4S | #16 |
1D | #8 |
2D | #16 |
Table 20-19 LD1 (Two registers, immediate offset) specifier combinations
T |
imm |
---|---|
8B | #16 |
16B | #32 |
4H | #16 |
8H | #32 |
2S | #16 |
4S | #32 |
1D | #16 |
2D | #32 |
Table 20-20 LD1 (Three registers, immediate offset) specifier combinations
T |
imm |
---|---|
8B | #24 |
16B | #48 |
4H | #24 |
8H | #48 |
2S | #24 |
4S | #48 |
1D | #24 |
2D | #48 |
Table 20-21 LD1 (Four registers, immediate offset) specifier combinations
T |
imm |
---|---|
8B | #32 |
16B | #64 |
4H | #32 |
8H | #64 |
2S | #32 |
4S | #64 |
1D | #32 |
2D | #64 |