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Home > A64 SIMD Vector Instructions > LD4R (vector) |
Load single 4-element structure and Replicate to all lanes of four registers.
LD4R {
Vt
.T
, Vt2
.T
, Vt3
.T
, Vt4
.T
}, [Xn|SP
] ; No offset
LD4R {
Vt
.T
, Vt2
.T
, Vt3
.T
, Vt4
.T
}, [Xn|SP
], imm
; Immediate offset, Post-index
LD4R {
Vt
.T
, Vt2
.T
, Vt3
.T
, Vt4
.T
}, [Xn|SP
], Xm
; Register offset, Post-index
Where:
Vt
Vt2
Vt3
Vt4
imm
Xm
T
Xn|SP
Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD and FP registers.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
The following table shows the valid specifier combinations:
Table 20-25 LD4R (Immediate offset) specifier combinations
T |
imm |
---|---|
8B | #4 |
16B | #4 |
4H | #8 |
8H | #8 |
2S | #16 |
4S | #16 |
1D | #32 |
2D | #32 |