ARM Compiler armasm User Guide : 20.112 LD4R (vector)

20.112 LD4R (vector)

Load single 4-element structure and Replicate to all lanes of four registers.

Syntax

LD4R { Vt.T, Vt2.T, Vt3.T, Vt4.T }, [Xn|SP] ; No offset

LD4R { Vt.T, Vt2.T, Vt3.T, Vt4.T }, [Xn|SP], imm ; Immediate offset, Post-index

LD4R { Vt.T, Vt2.T, Vt3.T, Vt4.T }, [Xn|SP], Xm ; Register offset, Post-index

Where:

Vt: Is the name of the first or only SIMD and FP register to be transferred.
Vt2: Is the name of the second SIMD and FP register to be transferred.
Vt3: Is the name of the third SIMD and FP register to be transferred.
Vt4: Is the name of the fourth SIMD and FP register to be transferred.
imm: Is the post-index immediate offset, and can be one of the values shown in Usage.
Xm: Is the 64-bit name of the general-purpose post-index register, excluding XZR.
T: Is an arrangement specifier, and can be one of the values shown in Usage.
Xn|SP: Is the 64-bit name of the general-purpose base register or stack pointer.

Usage

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD and FP registers.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

The following table shows the valid specifier combinations:

Table 20-25 LD4R (Immediate offset) specifier combinations

`T`	`imm`
8B	#4
16B	#4
4H	#8
8H	#8
2S	#16
4S	#16
1D	#32
2D	#32

Related reference

20.1 A64 SIMD Vector instructions in alphabetical order

Non-Confidential	PDF version	ARM 100069_0608_00_en
Copyright © 2014–2017 ARM Limited or its affiliates. All rights reserved.