20.146 SADDLP (vector)

Signed Add Long Pairwise.

Syntax

SADDLP Vd.Ta, Vn.Tb

Where:

Vd
Is the name of the SIMD and FP destination register.
Ta
Is an arrangement specifier, and can be one of the values shown in Usage.
Vn
Is the name of the SIMD and FP source register.
Tb
Is an arrangement specifier, and can be one of the values shown in Usage.

Usage

Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD and FP register, places the result into a vector, and writes the vector to the destination SIMD and FP register. The destination vector elements are twice as long as the source vector elements.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

The following table shows the valid specifier combinations:

Table 20-39 SADDLP (Vector) specifier combinations

Ta Tb
4H 8B
8H 16B
2S 4H
4S 8H
1D 2S
2D 4S
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