20.209 SSUBL, SSUBL2 (vector)

Signed Subtract Long.

Syntax

SSUBL{2} Vd.Ta, Vn.Tb, Vm.Tb

Where:

2
Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements. See <Q> in the Usage table.
Vd
Is the name of the SIMD and FP destination register.
Ta
Is an arrangement specifier, and can be one of the values shown in Usage.
Vn
Is the name of the first SIMD and FP source register.
Tb
Is an arrangement specifier, and can be one of the values shown in Usage.
Vm
Is the name of the second SIMD and FP source register.

Usage

Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD and FP register from the corresponding vector element of the first source SIMD and FP register, places the results into a vector, and writes the vector to the destination SIMD and FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.

The SSUBL instruction extracts each source vector from the lower half of each source register, while the SSUBL2 instruction extracts each source vector from the upper half of each source register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

The following table shows the valid specifier combinations:

Table 20-81 SSUBL, SSUBL2 (Vector) specifier combinations

<Q> Ta Tb
- 8H 8B
2 8H 16B
- 4S 4H
2 4S 8H
- 2D 2S
2 2D 4S
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