18.20 FCVTZS (scalar, integer)

Floating-point Convert to Signed integer, rounding toward Zero (scalar).

Syntax

FCVTZS Wd, Hn ; Half-precision to 32-bit

FCVTZS Xd, Hn ; Half-precision to 64-bit

FCVTZS Wd, Sn ; Single-precision to 32-bit

FCVTZS Xd, Sn ; Single-precision to 64-bit

FCVTZS Wd, Dn ; Double-precision to 32-bit

FCVTZS Xd, Dn ; Double-precision to 64-bit

Where:

Wd
Is the 32-bit name of the general-purpose destination register.
Hn
Is the 16-bit name of the SIMD and FP source register.
Xd
Is the 64-bit name of the general-purpose destination register.
Sn
Is the 32-bit name of the SIMD and FP source register.
Dn
Is the 64-bit name of the SIMD and FP source register.

Operation

Floating-point Convert to Signed integer, rounding toward Zero (scalar). This instruction converts the floating-point value in the SIMD and FP source register to a 32-bit or 64-bit signed integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.

A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Rd = signed_convertToIntegerExactTowardZero(Vn), where R is either W or X.

Non-ConfidentialPDF file icon PDF versionARM 100069_0608_00_en
Copyright © 2014–2017 ARM Limited or its affiliates. All rights reserved.