ARM Compiler armasm User Guide : 18.23 FDIV (scalar)

18.23 FDIV (scalar)

Floating-point Divide (scalar).

Syntax

FDIV Hd, Hn, Hm ; Half-precision

FDIV Sd, Sn, Sm ; Single-precision

FDIV Dd, Dn, Dm ; Double-precision

Where:

Hd: Is the 16-bit name of the SIMD and FP destination register.
Hn: Is the 16-bit name of the first SIMD and FP source register.
Hm: Is the 16-bit name of the second SIMD and FP source register.
Sd: Is the 32-bit name of the SIMD and FP destination register.
Sn: Is the 32-bit name of the first SIMD and FP source register.
Sm: Is the 32-bit name of the second SIMD and FP source register.
Dd: Is the 64-bit name of the SIMD and FP destination register.
Dn: Is the 64-bit name of the first SIMD and FP source register.
Dm: Is the 64-bit name of the second SIMD and FP source register.

Operation

Floating-point Divide (scalar). This instruction divides the floating-point value of the first source SIMD and FP register by the floating-point value of the second source SIMD and FP register, and writes the result to the destination SIMD and FP register.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Vd = Vn / Vm.

Related reference

18.1 A64 floating-point instructions in alphabetical order

Related information

ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile

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