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Home > A64 Floating-point Instructions > FDIV (scalar) |
Floating-point Divide (scalar).
FDIV
Hd
, Hn
, Hm
; Half-precision
FDIV
Sd
, Sn
, Sm
; Single-precision
FDIV
Dd
, Dn
, Dm
; Double-precision
Where:
Hd
Hn
Hm
Sd
Sn
Sm
Dd
Dn
Dm
Floating-point Divide (scalar). This instruction divides the floating-point value of the first source SIMD and FP register by the floating-point value of the second source SIMD and FP register, and writes the result to the destination SIMD and FP register.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
.V
d = V
n / Vm