18.55 SCVTF (scalar, integer)

Signed integer Convert to Floating-point (scalar).

Syntax

SCVTF Hd, Wn ; 32-bit to half-precision

SCVTF Sd, Wn ; 32-bit to single-precision

SCVTF Dd, Wn ; 32-bit to double-precision

SCVTF Hd, Xn ; 64-bit to half-precision

SCVTF Sd, Xn ; 64-bit to single-precision

SCVTF Dd, Xn ; 64-bit to double-precision

Where:

Hd
Is the 16-bit name of the SIMD and FP destination register.
Wn
Is the 32-bit name of the general-purpose source register.
Sd
Is the 32-bit name of the SIMD and FP destination register.
Dd
Is the 64-bit name of the SIMD and FP destination register.
Xn
Is the 64-bit name of the general-purpose source register.

Operation

Signed integer Convert to Floating-point (scalar). This instruction converts the signed integer value in the general-purpose source register to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD and FP destination register.

A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Vd = signed_convertFromInt(Rn), where R is either W or X.

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