ARM Compiler armasm User Guide : 16.33 BICS (shifted register)

16.33 BICS (shifted register)

Bitwise Bit Clear (shifted register), setting flags.

Syntax

BICS Wd, Wn, Wm{, shift #amount} ; 32-bit

BICS Xd, Xn, Xm{, shift #amount} ; 64-bit

Where:

Wd

Is the 32-bit name of the general-purpose destination register.

Wn

Is the 32-bit name of the first general-purpose source register.

Wm

Is the 32-bit name of the second general-purpose source register.

amount

Depends on the instruction variant:

32-bit general registers: Is the shift amount, in the range 0 to 31, defaulting to 0.
64-bit general registers: Is the shift amount, in the range 0 to 63, defaulting to 0.

Xd

Is the 64-bit name of the general-purpose destination register.

Xn

Is the 64-bit name of the first general-purpose source register.

Xm

Is the 64-bit name of the second general-purpose source register.

shift

Is the optional shift to be applied to the final source, defaulting to LSL, and can be one of LSL, LSR, ASR, or ROR.

Operation

Bitwise Bit Clear (shifted register), setting flags, performs a bitwise AND of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register. It updates the condition flags based on the result.

Rd = Rn AND NOT shift(Rm, amount), where R is either W or X.

Related reference

16.1 A64 instructions in alphabetical order

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