13.32 CRC32C

CRC32C performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register.

Syntax

CRC32CB{q} Rd, Rn, Rm ; A1 Wd = CRC32C(Wn, Rm[<7:0>])

CRC32CH{q} Rd, Rn, Rm ; A1 Wd = CRC32C(Wn, Rm[<15:0>])

CRC32CW{q} Rd, Rn, Rm ; A1 Wd = CRC32C(Wn, Rm[<31:0>])

CRC32CB{q} Rd, Rn, Rm ; T1 Wd = CRC32C(Wn, Rm[<7:0>])

CRC32CH{q} Rd, Rn, Rm ; T1 Wd = CRC32C(Wn, Rm[<15:0>])

CRC32CW{q} Rd, Rn, Rm ; T1 Wd = CRC32C(Wn, Rm[<31:0>])

Where:

q
Is an optional instruction width specifier. See 13.2 Instruction width specifiers. A CRC32C instruction must be unconditional.
Rd
Is the general-purpose accumulator output register.
Rn
Is the general-purpose accumulator input register.
Rm
Is the general-purpose data source register.

Architectures supported

Supported in architecture ARMv8.1 and later. Optionally supported in ARMv8-A.

Usage

CRC32C takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, or 32 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x1EDC6F41 is used for the CRC calculation.

Note:

ID_ISAR5.CRC32 indicates whether this instruction is supported in the T32 and A32 instruction sets.

Note:

For more information about the constrained unpredictable behavior, see Architectural Constraints on UNPREDICTABLE behaviors in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.
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