17.67 LDUMINAH, LDUMINALH, LDUMINH, LDUMINLH

Atomic unsigned minimum on halfword in memory.

Syntax

LDUMINAH Ws, Wt, [Xn|SP] ; Acquire general registers

LDUMINALH Ws, Wt, [Xn|SP] ; Acquire and release general registers

LDUMINH Ws, Wt, [Xn|SP] ; No memory ordering general registers

LDUMINLH Ws, Wt, [Xn|SP] ; Release general registers

Where:

Ws
Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location.
Wt
Is the 32-bit name of the general-purpose register to be loaded.
Xn|SP
Is the 64-bit name of the general-purpose base register or stack pointer.

Architectures supported

Supported in ARMv8.1 and later.

Usage

Atomic unsigned minimum on halfword in memory atomically loads a 16-bit halfword from memory, compares it against the value held in a register, and stores the smaller value back to memory, treating the values as unsigned numbers. The value initially loaded from memory is returned in the destination register.

  • If the destination register is not WZR, LDUMINAH and LDUMINALH load from memory with acquire semantics.
  • LDUMINLH and LDUMINALH store to memory with release semantics.
  • LDUMINH has no memory ordering requirements.

For more information about memory ordering semantics see Load-Acquire, Store-Release in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

For information about memory accesses see Load/Store addressing modes in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

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