14.22 VCADD

Vector Complex Add.

Syntax

VCADD{q}.dt {Dd,} Dn, Dm, #rotate ; A1 64-bit SIMD vector FP/SIMD registers (A32)

VCADD{q}.dt {Qd,} Qn, Qm, #rotate ; A1 128-bit SIMD vector FP/SIMD registers (A32)

Where:

Dd
Is the 64-bit name of the SIMD and FP destination register.
Dn
Is the 64-bit name of the first SIMD and FP source register.
Dm
Is the 64-bit name of the second SIMD and FP source register.
Qd
Is the 128-bit name of the SIMD and FP destination register.
Qn
Is the 128-bit name of the first SIMD and FP source register.
Qm
Is the 128-bit name of the second SIMD and FP source register.
q
Is an optional instruction width specifier. See 13.2 Instruction width specifiers.
dt
Is the data type for the elements of the vectors, and can be either F16 or F32.
rotate
Is the rotation to be applied to elements in the second SIMD and FP source register, and can be either 90 or 270.

Architectures supported

Supported in ARMv8.3.

Usage

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support in the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

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