Arm® Instruction Set Reference Guide

Version 1.0


Table of Contents

Preface
About this book
Using this book
Glossary
Typographic conventions
Feedback
Feedback on this product
Feedback on content
Other information
Part A Instruction Set Overview
A1 Overview of the Arm® Architecture
A1.1 About the Arm® architecture
A1.2 Differences between the A64, A32, and T32 instruction sets
A1.3 Changing between AArch64 and AArch32 states
A1.4 Advanced SIMD
A1.5 Floating-point hardware
A2 Overview of AArch32 state
A2.1 Changing between A32 and T32 instruction set states
A2.2 Processor modes, and privileged and unprivileged software execution
A2.3 Processor modes in Armv6‑M, Armv7‑M, and Armv8‑M
A2.4 Registers in AArch32 state
A2.5 General-purpose registers in AArch32 state
A2.6 Register accesses in AArch32 state
A2.7 Predeclared core register names in AArch32 state
A2.8 Predeclared extension register names in AArch32 state
A2.9 Program Counter in AArch32 state
A2.10 The Q flag in AArch32 state
A2.11 Application Program Status Register
A2.12 Current Program Status Register in AArch32 state
A2.13 Saved Program Status Registers in AArch32 state
A2.14 A32 and T32 instruction set overview
A2.15 Access to the inline barrel shifter in AArch32 state
A3 Overview of AArch64 state
A3.1 Registers in AArch64 state
A3.2 Exception levels
A3.3 Link registers
A3.4 Stack Pointer register
A3.5 Predeclared core register names in AArch64 state
A3.6 Predeclared extension register names in AArch64 state
A3.7 Program Counter in AArch64 state
A3.8 Conditional execution in AArch64 state
A3.9 The Q flag in AArch64 state
A3.10 Process State
A3.11 Saved Program Status Registers in AArch64 state
A3.12 A64 instruction set overview
Part B Advanced SIMD and Floating-point Programming
B1 Advanced SIMD Programming
B1.1 Architecture support for Advanced SIMD
B1.2 Extension register bank mapping for Advanced SIMD in AArch32 state
B1.3 Extension register bank mapping for Advanced SIMD in AArch64 state
B1.4 Views of the Advanced SIMD register bank in AArch32 state
B1.5 Views of the Advanced SIMD register bank in AArch64 state
B1.6 Differences between A32/T32 and A64 Advanced SIMD instruction syntax
B1.7 Load values to Advanced SIMD registers
B1.8 Conditional execution of A32/T32 Advanced SIMD instructions
B1.9 Floating-point exceptions for Advanced SIMD in A32/T32 instructions
B1.10 Advanced SIMD data types in A32/T32 instructions
B1.11 Polynomial arithmetic over {0,1}
B1.12 Advanced SIMD vectors
B1.13 Normal, long, wide, and narrow Advanced SIMD instructions
B1.14 Saturating Advanced SIMD instructions
B1.15 Advanced SIMD scalars
B1.16 Extended notation extension for Advanced SIMD in A32/T32 code
B1.17 Advanced SIMD system registers in AArch32 state
B1.18 Flush-to-zero mode in Advanced SIMD
B1.19 When to use flush-to-zero mode in Advanced SIMD
B1.20 The effects of using flush-to-zero mode in Advanced SIMD
B1.21 Advanced SIMD operations not affected by flush-to-zero mode
B2 Floating-point Programming
B2.1 Architecture support for floating-point
B2.2 Extension register bank mapping for floating-point in AArch32 state
B2.3 Extension register bank mapping in AArch64 state
B2.4 Views of the floating-point extension register bank in AArch32 state
B2.5 Views of the floating-point extension register bank in AArch64 state
B2.6 Differences between A32/T32 and A64 floating-point instruction syntax
B2.7 Load values to floating-point registers
B2.8 Conditional execution of A32/T32 floating-point instructions
B2.9 Floating-point exceptions for floating-point in A32/T32 instructions
B2.10 Floating-point data types in A32/T32 instructions
B2.11 Extended notation extension for floating-point in A32/T32 code
B2.12 Floating-point system registers in AArch32 state
B2.13 Flush-to-zero mode in floating-point
B2.14 When to use flush-to-zero mode in floating-point
B2.15 The effects of using flush-to-zero mode in floating-point
B2.16 Floating-point operations not affected by flush-to-zero mode
Part C A32/T32 Instruction Set Reference
C1 Condition Codes
C1.1 Conditional instructions
C1.2 Conditional execution in A32 code
C1.3 Conditional execution in T32 code
C1.4 Condition flags
C1.5 Updates to the condition flags in A32/T32 code
C1.6 Floating-point instructions that update the condition flags
C1.7 Carry flag
C1.8 Overflow flag
C1.9 Condition code suffixes
C1.10 Condition code suffixes and related flags
C1.11 Comparison of condition code meanings in integer and floating-point code
C1.12 Benefits of using conditional execution in A32 and T32 code
C1.13 Example showing the benefits of conditional instructions in A32 and T32 code
C1.14 Optimization for execution speed
C2 A32 and T32 Instructions
C2.1 A32 and T32 instruction summary
C2.2 Instruction width specifiers
C2.3 Flexible second operand (Operand2)
C2.4 Syntax of Operand2 as a constant
C2.5 Syntax of Operand2 as a register with optional shift
C2.6 Shift operations
C2.7 Saturating instructions
C2.8 ADC
C2.9 ADD
C2.10 ADR (PC-relative)
C2.11 ADR (register-relative)
C2.12 AND
C2.13 ASR
C2.14 B
C2.15 BFC
C2.16 BFI
C2.17 BIC
C2.18 BKPT
C2.19 BL
C2.20 BLX, BLXNS
C2.21 BX, BXNS
C2.22 BXJ
C2.23 CBZ and CBNZ
C2.24 CDP and CDP2
C2.25 CLREX
C2.26 CLZ
C2.27 CMP and CMN
C2.28 CPS
C2.29 CRC32
C2.30 CRC32C
C2.31 CSDB
C2.32 DBG
C2.33 DCPS1 (T32 instruction)
C2.34 DCPS2 (T32 instruction)
C2.35 DCPS3 (T32 instruction)
C2.36 DMB
C2.37 DSB
C2.38 EOR
C2.39 ERET
C2.40 ESB
C2.41 HLT
C2.42 HVC
C2.43 ISB
C2.44 IT
C2.45 LDA
C2.46 LDAEX
C2.47 LDC and LDC2
C2.48 LDM
C2.49 LDR (immediate offset)
C2.50 LDR (PC-relative)
C2.51 LDR (register offset)
C2.52 LDR (register-relative)
C2.53 LDR, unprivileged
C2.54 LDREX
C2.55 LSL
C2.56 LSR
C2.57 MCR and MCR2
C2.58 MCRR and MCRR2
C2.59 MLA
C2.60 MLS
C2.61 MOV
C2.62 MOVT
C2.63 MRC and MRC2
C2.64 MRRC and MRRC2
C2.65 MRS (PSR to general-purpose register)
C2.66 MRS (system coprocessor register to general-purpose register)
C2.67 MSR (general-purpose register to system coprocessor register)
C2.68 MSR (general-purpose register to PSR)
C2.69 MUL
C2.70 MVN
C2.71 NOP
C2.72 ORN (T32 only)
C2.73 ORR
C2.74 PKHBT and PKHTB
C2.75 PLD, PLDW, and PLI
C2.76 POP
C2.77 PUSH
C2.78 QADD
C2.79 QADD8
C2.80 QADD16
C2.81 QASX
C2.82 QDADD
C2.83 QDSUB
C2.84 QSAX
C2.85 QSUB
C2.86 QSUB8
C2.87 QSUB16
C2.88 RBIT
C2.89 REV
C2.90 REV16
C2.91 REVSH
C2.92 RFE
C2.93 ROR
C2.94 RRX
C2.95 RSB
C2.96 RSC
C2.97 SADD8
C2.98 SADD16
C2.99 SASX
C2.100 SBC
C2.101 SBFX
C2.102 SDIV
C2.103 SEL
C2.104 SETEND
C2.105 SETPAN
C2.106 SEV
C2.107 SEVL
C2.108 SG
C2.109 SHADD8
C2.110 SHADD16
C2.111 SHASX
C2.112 SHSAX
C2.113 SHSUB8
C2.114 SHSUB16
C2.115 SMC
C2.116 SMLAxy
C2.117 SMLAD
C2.118 SMLAL
C2.119 SMLALD
C2.120 SMLALxy
C2.121 SMLAWy
C2.122 SMLSD
C2.123 SMLSLD
C2.124 SMMLA
C2.125 SMMLS
C2.126 SMMUL
C2.127 SMUAD
C2.128 SMULxy
C2.129 SMULL
C2.130 SMULWy
C2.131 SMUSD
C2.132 SRS
C2.133 SSAT
C2.134 SSAT16
C2.135 SSAX
C2.136 SSUB8
C2.137 SSUB16
C2.138 STC and STC2
C2.139 STL
C2.140 STLEX
C2.141 STM
C2.142 STR (immediate offset)
C2.143 STR (register offset)
C2.144 STR, unprivileged
C2.145 STREX
C2.146 SUB
C2.147 SUBS pc, lr
C2.148 SVC
C2.149 SWP and SWPB
C2.150 SXTAB
C2.151 SXTAB16
C2.152 SXTAH
C2.153 SXTB
C2.154 SXTB16
C2.155 SXTH
C2.156 SYS
C2.157 TBB and TBH
C2.158 TEQ
C2.159 TST
C2.160 TT, TTT, TTA, TTAT
C2.161 UADD8
C2.162 UADD16
C2.163 UASX
C2.164 UBFX
C2.165 UDF
C2.166 UDIV
C2.167 UHADD8
C2.168 UHADD16
C2.169 UHASX
C2.170 UHSAX
C2.171 UHSUB8
C2.172 UHSUB16
C2.173 UMAAL
C2.174 UMLAL
C2.175 UMULL
C2.176 UQADD8
C2.177 UQADD16
C2.178 UQASX
C2.179 UQSAX
C2.180 UQSUB8
C2.181 UQSUB16
C2.182 USAD8
C2.183 USADA8
C2.184 USAT
C2.185 USAT16
C2.186 USAX
C2.187 USUB8
C2.188 USUB16
C2.189 UXTAB
C2.190 UXTAB16
C2.191 UXTAH
C2.192 UXTB
C2.193 UXTB16
C2.194 UXTH
C2.195 WFE
C2.196 WFI
C2.197 YIELD
C3 Advanced SIMD Instructions (32-bit)
C3.1 Summary of Advanced SIMD instructions
C3.2 Summary of shared Advanced SIMD and floating-point instructions
C3.3 Interleaving provided by load and store element and structure instructions
C3.4 Alignment restrictions in load and store element and structure instructions
C3.5 FLDMDBX, FLDMIAX
C3.6 FSTMDBX, FSTMIAX
C3.7 VABA and VABAL
C3.8 VABD and VABDL
C3.9 VABS
C3.10 VACLE, VACLT, VACGE and VACGT
C3.11 VADD
C3.12 VADDHN
C3.13 VADDL and VADDW
C3.14 VAND (immediate)
C3.15 VAND (register)
C3.16 VBIC (immediate)
C3.17 VBIC (register)
C3.18 VBIF
C3.19 VBIT
C3.20 VBSL
C3.21 VCADD
C3.22 VCEQ (immediate #0)
C3.23 VCEQ (register)
C3.24 VCGE (immediate #0)
C3.25 VCGE (register)
C3.26 VCGT (immediate #0)
C3.27 VCGT (register)
C3.28 VCLE (immediate #0)
C3.29 VCLS
C3.30 VCLE (register)
C3.31 VCLT (immediate #0)
C3.32 VCLT (register)
C3.33 VCLZ
C3.34 VCMLA
C3.35 VCMLA (by element)
C3.36 VCNT
C3.37 VCVT (between fixed-point or integer, and floating-point)
C3.38 VCVT (between half-precision and single-precision floating-point)
C3.39 VCVT (from floating-point to integer with directed rounding modes)
C3.40 VCVTB, VCVTT (between half-precision and double-precision)
C3.41 VDUP
C3.42 VEOR
C3.43 VEXT
C3.44 VFMA, VFMS
C3.45 VFMAL (by scalar)
C3.46 VFMAL (vector)
C3.47 VFMSL (by scalar)
C3.48 VFMSL (vector)
C3.49 VHADD
C3.50 VHSUB
C3.51 VLDn (single n-element structure to one lane)
C3.52 VLDn (single n-element structure to all lanes)
C3.53 VLDn (multiple n-element structures)
C3.54 VLDM
C3.55 VLDR
C3.56 VLDR (post-increment and pre-decrement)
C3.57 VLDR pseudo-instruction
C3.58 VMAX and VMIN
C3.59 VMAXNM, VMINNM
C3.60 VMLA
C3.61 VMLA (by scalar)
C3.62 VMLAL (by scalar)
C3.63 VMLAL
C3.64 VMLS (by scalar)
C3.65 VMLS
C3.66 VMLSL
C3.67 VMLSL (by scalar)
C3.68 VMOV (immediate)
C3.69 VMOV (register)
C3.70 VMOV (between two general-purpose registers and a 64-bit extension register)
C3.71 VMOV (between a general-purpose register and an Advanced SIMD scalar)
C3.72 VMOVL
C3.73 VMOVN
C3.74 VMOV2
C3.75 VMRS
C3.76 VMSR
C3.77 VMUL
C3.78 VMUL (by scalar)
C3.79 VMULL
C3.80 VMULL (by scalar)
C3.81 VMVN (register)
C3.82 VMVN (immediate)
C3.83 VNEG
C3.84 VORN (register)
C3.85 VORN (immediate)
C3.86 VORR (register)
C3.87 VORR (immediate)
C3.88 VPADAL
C3.89 VPADD
C3.90 VPADDL
C3.91 VPMAX and VPMIN
C3.92 VPOP
C3.93 VPUSH
C3.94 VQABS
C3.95 VQADD
C3.96 VQDMLAL and VQDMLSL (by vector or by scalar)
C3.97 VQDMULH (by vector or by scalar)
C3.98 VQDMULL (by vector or by scalar)
C3.99 VQMOVN and VQMOVUN
C3.100 VQNEG
C3.101 VQRDMULH (by vector or by scalar)
C3.102 VQRSHL (by signed variable)
C3.103 VQRSHRN and VQRSHRUN (by immediate)
C3.104 VQSHL (by signed variable)
C3.105 VQSHL and VQSHLU (by immediate)
C3.106 VQSHRN and VQSHRUN (by immediate)
C3.107 VQSUB
C3.108 VRADDHN
C3.109 VRECPE
C3.110 VRECPS
C3.111 VREV16, VREV32, and VREV64
C3.112 VRHADD
C3.113 VRSHL (by signed variable)
C3.114 VRSHR (by immediate)
C3.115 VRSHRN (by immediate)
C3.116 VRINT
C3.117 VRSQRTE
C3.118 VRSQRTS
C3.119 VRSRA (by immediate)
C3.120 VRSUBHN
C3.121 VSDOT (vector)
C3.122 VSDOT (by element)
C3.123 VSHL (by immediate)
C3.124 VSHL (by signed variable)
C3.125 VSHLL (by immediate)
C3.126 VSHR (by immediate)
C3.127 VSHRN (by immediate)
C3.128 VSLI
C3.129 VSRA (by immediate)
C3.130 VSRI
C3.131 VSTM
C3.132 VSTn (multiple n-element structures)
C3.133 VSTn (single n-element structure to one lane)
C3.134 VSTR
C3.135 VSTR (post-increment and pre-decrement)
C3.136 VSUB
C3.137 VSUBHN
C3.138 VSUBL and VSUBW
C3.139 VSWP
C3.140 VTBL and VTBX
C3.141 VTRN
C3.142 VTST
C3.143 VUDOT (vector)
C3.144 VUDOT (by element)
C3.145 VUZP
C3.146 VZIP
C4 Floating-point Instructions (32-bit)
C4.1 Summary of floating-point instructions
C4.2 VABS (floating-point)
C4.3 VADD (floating-point)
C4.4 VCMP, VCMPE
C4.5 VCVT (between single-precision and double-precision)
C4.6 VCVT (between floating-point and integer)
C4.7 VCVT (from floating-point to integer with directed rounding modes)
C4.8 VCVT (between floating-point and fixed-point)
C4.9 VCVTB, VCVTT (half-precision extension)
C4.10 VCVTB, VCVTT (between half-precision and double-precision)
C4.11 VDIV
C4.12 VFMA, VFMS, VFNMA, VFNMS (floating-point)
C4.13 VJCVT
C4.14 VLDM (floating-point)
C4.15 VLDR (floating-point)
C4.16 VLDR (post-increment and pre-decrement, floating-point)
C4.17 VLLDM
C4.18 VLSTM
C4.19 VMAXNM, VMINNM (floating-point)
C4.20 VMLA (floating-point)
C4.21 VMLS (floating-point)
C4.22 VMOV (floating-point)
C4.23 VMOV (between one general-purpose register and single precision floating-point register)
C4.24 VMOV (between two general-purpose registers and one or two extension registers)
C4.25 VMOV (between a general-purpose register and half a double precision floating-point register)
C4.26 VMRS (floating-point)
C4.27 VMSR (floating-point)
C4.28 VMUL (floating-point)
C4.29 VNEG (floating-point)
C4.30 VNMLA (floating-point)
C4.31 VNMLS (floating-point)
C4.32 VNMUL (floating-point)
C4.33 VPOP (floating-point)
C4.34 VPUSH (floating-point)
C4.35 VRINT (floating-point)
C4.36 VSEL
C4.37 VSQRT
C4.38 VSTM (floating-point)
C4.39 VSTR (floating-point)
C4.40 VSTR (post-increment and pre-decrement, floating-point)
C4.41 VSUB (floating-point)
C5 A32/T32 Cryptographic Algorithms
C5.1 A32/T32 Cryptographic instructions
Part D A64 Instruction Set Reference
D1 Condition Codes
D1.1 Conditional execution in A64 code
D1.2 Condition flags
D1.3 Updates to the condition flags in A64 code
D1.4 Floating-point instructions that update the condition flags
D1.5 Carry flag
D1.6 Overflow flag
D1.7 Condition code suffixes
D1.8 Condition code suffixes and related flags
D1.9 Optimization for execution speed
D2 A64 General Instructions
D2.1 A64 instructions in alphabetical order
D2.2 Register restrictions for A64 instructions
D2.3 ADC
D2.4 ADCS
D2.5 ADD (extended register)
D2.6 ADD (immediate)
D2.7 ADD (shifted register)
D2.8 ADDG
D2.9 ADDS (extended register)
D2.10 ADDS (immediate)
D2.11 ADDS (shifted register)
D2.12 ADR
D2.13 ADRP
D2.14 AND (immediate)
D2.15 AND (shifted register)
D2.16 ANDS (immediate)
D2.17 ANDS (shifted register)
D2.18 ASR (register)
D2.19 ASR (immediate)
D2.20 ASRV
D2.21 AT
D2.22 AUTDA, AUTDZA
D2.23 AUTDB, AUTDZB
D2.24 AUTIA, AUTIZA, AUTIA1716, AUTIASP, AUTIAZ
D2.25 AUTIB, AUTIZB, AUTIB1716, AUTIBSP, AUTIBZ
D2.26 AXFlag
D2.27 B.cond
D2.28 B
D2.29 BFC
D2.30 BFI
D2.31 BFM
D2.32 BFXIL
D2.33 BIC (shifted register)
D2.34 BICS (shifted register)
D2.35 BL
D2.36 BLR
D2.37 BLRAA, BLRAAZ, BLRAB, BLRABZ
D2.38 BR
D2.39 BRAA, BRAAZ, BRAB, BRABZ
D2.40 BRK
D2.41 BTI
D2.42 CBNZ
D2.43 CBZ
D2.44 CCMN (immediate)
D2.45 CCMN (register)
D2.46 CCMP (immediate)
D2.47 CCMP (register)
D2.48 CINC
D2.49 CINV
D2.50 CLREX
D2.51 CLS
D2.52 CLZ
D2.53 CMN (extended register)
D2.54 CMN (immediate)
D2.55 CMN (shifted register)
D2.56 CMP (extended register)
D2.57 CMP (immediate)
D2.58 CMP (shifted register)
D2.59 CMPP
D2.60 CNEG
D2.61 CRC32B, CRC32H, CRC32W, CRC32X
D2.62 CRC32CB, CRC32CH, CRC32CW, CRC32CX
D2.63 CSDB
D2.64 CSEL
D2.65 CSET
D2.66 CSETM
D2.67 CSINC
D2.68 CSINV
D2.69 CSNEG
D2.70 DC
D2.71 DCPS1
D2.72 DCPS2
D2.73 DCPS3
D2.74 DMB
D2.75 DRPS
D2.76 DSB
D2.77 EON (shifted register)
D2.78 EOR (immediate)
D2.79 EOR (shifted register)
D2.80 ERET
D2.81 ERETAA, ERETAB
D2.82 ESB
D2.83 EXTR
D2.84 GMI
D2.85 HINT
D2.86 HLT
D2.87 HVC
D2.88 IC
D2.89 IRG
D2.90 ISB
D2.91 LDG
D2.92 LDGV
D2.93 LSL (register)
D2.94 LSL (immediate)
D2.95 LSLV
D2.96 LSR (register)
D2.97 LSR (immediate)
D2.98 LSRV
D2.99 MADD
D2.100 MNEG
D2.101 MOV (to or from SP)
D2.102 MOV (inverted wide immediate)
D2.103 MOV (wide immediate)
D2.104 MOV (bitmask immediate)
D2.105 MOV (register)
D2.106 MOVK
D2.107 MOVN
D2.108 MOVZ
D2.109 MRS
D2.110 MSR (immediate)
D2.111 MSR (register)
D2.112 MSUB
D2.113 MUL
D2.114 MVN
D2.115 NEG (shifted register)
D2.116 NEGS
D2.117 NGC
D2.118 NGCS
D2.119 NOP
D2.120 ORN (shifted register)
D2.121 ORR (immediate)
D2.122 ORR (shifted register)
D2.123 PACDA, PACDZA
D2.124 PACDB, PACDZB
D2.125 PACGA
D2.126 PACIA, PACIZA, PACIA1716, PACIASP, PACIAZ
D2.127 PACIB, PACIZB, PACIB1716, PACIBSP, PACIBZ
D2.128 PSB
D2.129 RBIT
D2.130 RET
D2.131 RETAA, RETAB
D2.132 REV16
D2.133 REV32
D2.134 REV64
D2.135 REV
D2.136 ROR (immediate)
D2.137 ROR (register)
D2.138 RORV
D2.139 SBC
D2.140 SBCS
D2.141 SBFIZ
D2.142 SBFM
D2.143 SBFX
D2.144 SDIV
D2.145 SEV
D2.146 SEVL
D2.147 SMADDL
D2.148 SMC
D2.149 SMNEGL
D2.150 SMSUBL
D2.151 SMULH
D2.152 SMULL
D2.153 ST2G
D2.154 STG
D2.155 STGP
D2.156 STGV
D2.157 STZ2G
D2.158 STZG
D2.159 SUB (extended register)
D2.160 SUB (immediate)
D2.161 SUB (shifted register)
D2.162 SUBG
D2.163 SUBP
D2.164 SUBPS
D2.165 SUBS (extended register)
D2.166 SUBS (immediate)
D2.167 SUBS (shifted register)
D2.168 SVC
D2.169 SXTB
D2.170 SXTH
D2.171 SXTW
D2.172 SYS
D2.173 SYSL
D2.174 TBNZ
D2.175 TBZ
D2.176 TLBI
D2.177 TST (immediate)
D2.178 TST (shifted register)
D2.179 UBFIZ
D2.180 UBFM
D2.181 UBFX
D2.182 UDIV
D2.183 UMADDL
D2.184 UMNEGL
D2.185 UMSUBL
D2.186 UMULH
D2.187 UMULL
D2.188 UXTB
D2.189 UXTH
D2.190 XAFlag
D2.191 WFE
D2.192 WFI
D2.193 XPACD, XPACI, XPACLRI
D2.194 YIELD
D3 A64 Data Transfer Instructions
D3.1 A64 data transfer instructions in alphabetical order
D3.2 CASA, CASAL, CAS, CASL, CASAL, CAS, CASL
D3.3 CASAB, CASALB, CASB, CASLB
D3.4 CASAH, CASALH, CASH, CASLH
D3.5 CASPA, CASPAL, CASP, CASPL, CASPAL, CASP, CASPL
D3.6 LDADDA, LDADDAL, LDADD, LDADDL, LDADDAL, LDADD, LDADDL
D3.7 LDADDAB, LDADDALB, LDADDB, LDADDLB
D3.8 LDADDAH, LDADDALH, LDADDH, LDADDLH
D3.9 LDAPR
D3.10 LDAPRB
D3.11 LDAPRH
D3.12 LDAR
D3.13 LDARB
D3.14 LDARH
D3.15 LDAXP
D3.16 LDAXR
D3.17 LDAXRB
D3.18 LDAXRH
D3.19 LDCLRA, LDCLRAL, LDCLR, LDCLRL, LDCLRAL, LDCLR, LDCLRL
D3.20 LDCLRAB, LDCLRALB, LDCLRB, LDCLRLB
D3.21 LDCLRAH, LDCLRALH, LDCLRH, LDCLRLH
D3.22 LDEORA, LDEORAL, LDEOR, LDEORL, LDEORAL, LDEOR, LDEORL
D3.23 LDEORAB, LDEORALB, LDEORB, LDEORLB
D3.24 LDEORAH, LDEORALH, LDEORH, LDEORLH
D3.25 LDLAR
D3.26 LDLARB
D3.27 LDLARH
D3.28 LDNP
D3.29 LDP
D3.30 LDPSW
D3.31 LDR (immediate)
D3.32 LDR (literal)
D3.33 LDR (register)
D3.34 LDRAA, LDRAB, LDRAB
D3.35 LDRB (immediate)
D3.36 LDRB (register)
D3.37 LDRH (immediate)
D3.38 LDRH (register)
D3.39 LDRSB (immediate)
D3.40 LDRSB (register)
D3.41 LDRSH (immediate)
D3.42 LDRSH (register)
D3.43 LDRSW (immediate)
D3.44 LDRSW (literal)
D3.45 LDRSW (register)
D3.46 LDSETA, LDSETAL, LDSET, LDSETL, LDSETAL, LDSET, LDSETL
D3.47 LDSETAB, LDSETALB, LDSETB, LDSETLB
D3.48 LDSETAH, LDSETALH, LDSETH, LDSETLH
D3.49 LDSMAXA, LDSMAXAL, LDSMAX, LDSMAXL, LDSMAXAL, LDSMAX, LDSMAXL
D3.50 LDSMAXAB, LDSMAXALB, LDSMAXB, LDSMAXLB
D3.51 LDSMAXAH, LDSMAXALH, LDSMAXH, LDSMAXLH
D3.52 LDSMINA, LDSMINAL, LDSMIN, LDSMINL, LDSMINAL, LDSMIN, LDSMINL
D3.53 LDSMINAB, LDSMINALB, LDSMINB, LDSMINLB
D3.54 LDSMINAH, LDSMINALH, LDSMINH, LDSMINLH
D3.55 LDTR
D3.56 LDTRB
D3.57 LDTRH
D3.58 LDTRSB
D3.59 LDTRSH
D3.60 LDTRSW
D3.61 LDUMAXA, LDUMAXAL, LDUMAX, LDUMAXL, LDUMAXAL, LDUMAX, LDUMAXL
D3.62 LDUMAXAB, LDUMAXALB, LDUMAXB, LDUMAXLB
D3.63 LDUMAXAH, LDUMAXALH, LDUMAXH, LDUMAXLH
D3.64 LDUMINA, LDUMINAL, LDUMIN, LDUMINL, LDUMINAL, LDUMIN, LDUMINL
D3.65 LDUMINAB, LDUMINALB, LDUMINB, LDUMINLB
D3.66 LDUMINAH, LDUMINALH, LDUMINH, LDUMINLH
D3.67 LDUR
D3.68 LDURB
D3.69 LDURH
D3.70 LDURSB
D3.71 LDURSH
D3.72 LDURSW
D3.73 LDXP
D3.74 LDXR
D3.75 LDXRB
D3.76 LDXRH
D3.77 PRFM (immediate)
D3.78 PRFM (literal)
D3.79 PRFM (register)
D3.80 PRFUM (unscaled offset)
D3.81 STADD, STADDL, STADDL
D3.82 STADDB, STADDLB
D3.83 STADDH, STADDLH
D3.84 STCLR, STCLRL, STCLRL
D3.85 STCLRB, STCLRLB
D3.86 STCLRH, STCLRLH
D3.87 STEOR, STEORL, STEORL
D3.88 STEORB, STEORLB
D3.89 STEORH, STEORLH
D3.90 STLLR
D3.91 STLLRB
D3.92 STLLRH
D3.93 STLR
D3.94 STLRB
D3.95 STLRH
D3.96 STLXP
D3.97 STLXR
D3.98 STLXRB
D3.99 STLXRH
D3.100 STNP
D3.101 STP
D3.102 STR (immediate)
D3.103 STR (register)
D3.104 STRB (immediate)
D3.105 STRB (register)
D3.106 STRH (immediate)
D3.107 STRH (register)
D3.108 STSET, STSETL, STSETL
D3.109 STSETB, STSETLB
D3.110 STSETH, STSETLH
D3.111 STSMAX, STSMAXL, STSMAXL
D3.112 STSMAXB, STSMAXLB
D3.113 STSMAXH, STSMAXLH
D3.114 STSMIN, STSMINL, STSMINL
D3.115 STSMINB, STSMINLB
D3.116 STSMINH, STSMINLH
D3.117 STTR
D3.118 STTRB
D3.119 STTRH
D3.120 STUMAX, STUMAXL, STUMAXL
D3.121 STUMAXB, STUMAXLB
D3.122 STUMAXH, STUMAXLH
D3.123 STUMIN, STUMINL, STUMINL
D3.124 STUMINB, STUMINLB
D3.125 STUMINH, STUMINLH
D3.126 STUR
D3.127 STURB
D3.128 STURH
D3.129 STXP
D3.130 STXR
D3.131 STXRB
D3.132 STXRH
D3.133 SWPA, SWPAL, SWP, SWPL, SWPAL, SWP, SWPL
D3.134 SWPAB, SWPALB, SWPB, SWPLB
D3.135 SWPAH, SWPALH, SWPH, SWPLH
D4 A64 Floating-point Instructions
D4.1 A64 floating-point instructions in alphabetical order
D4.2 Register restrictions for A64 instructions
D4.3 FABS (scalar)
D4.4 FADD (scalar)
D4.5 FCCMP
D4.6 FCCMPE
D4.7 FCMP
D4.8 FCMPE
D4.9 FCSEL
D4.10 FCVT
D4.11 FCVTAS (scalar)
D4.12 FCVTAU (scalar)
D4.13 FCVTMS (scalar)
D4.14 FCVTMU (scalar)
D4.15 FCVTNS (scalar)
D4.16 FCVTNU (scalar)
D4.17 FCVTPS (scalar)
D4.18 FCVTPU (scalar)
D4.19 FCVTZS (scalar, fixed-point)
D4.20 FCVTZS (scalar, integer)
D4.21 FCVTZU (scalar, fixed-point)
D4.22 FCVTZU (scalar, integer)
D4.23 FDIV (scalar)
D4.24 FJCVTZS
D4.25 FMADD
D4.26 FMAX (scalar)
D4.27 FMAXNM (scalar)
D4.28 FMIN (scalar)
D4.29 FMINNM (scalar)
D4.30 FMOV (register)
D4.31 FMOV (general)
D4.32 FMOV (scalar, immediate)
D4.33 FMSUB
D4.34 FMUL (scalar)
D4.35 FNEG (scalar)
D4.36 FNMADD
D4.37 FNMSUB
D4.38 FNMUL (scalar)
D4.39 FRINTA (scalar)
D4.40 FRINTI (scalar)
D4.41 FRINTM (scalar)
D4.42 FRINTN (scalar)
D4.43 FRINTP (scalar)
D4.44 FRINTX (scalar)
D4.45 FRINTZ (scalar)
D4.46 FSQRT (scalar)
D4.47 FSUB (scalar)
D4.48 LDNP (SIMD and FP)
D4.49 LDP (SIMD and FP)
D4.50 LDR (immediate, SIMD and FP)
D4.51 LDR (literal, SIMD and FP)
D4.52 LDR (register, SIMD and FP)
D4.53 LDUR (SIMD and FP)
D4.54 SCVTF (scalar, fixed-point)
D4.55 SCVTF (scalar, integer)
D4.56 STNP (SIMD and FP)
D4.57 STP (SIMD and FP)
D4.58 STR (immediate, SIMD and FP)
D4.59 STR (register, SIMD and FP)
D4.60 STUR (SIMD and FP)
D4.61 UCVTF (scalar, fixed-point)
D4.62 UCVTF (scalar, integer)
D5 A64 SIMD Scalar Instructions
D5.1 A64 SIMD scalar instructions in alphabetical order
D5.2 ABS (scalar)
D5.3 ADD (scalar)
D5.4 ADDP (scalar)
D5.5 CMEQ (scalar, register)
D5.6 CMEQ (scalar, zero)
D5.7 CMGE (scalar, register)
D5.8 CMGE (scalar, zero)
D5.9 CMGT (scalar, register)
D5.10 CMGT (scalar, zero)
D5.11 CMHI (scalar, register)
D5.12 CMHS (scalar, register)
D5.13 CMLE (scalar, zero)
D5.14 CMLT (scalar, zero)
D5.15 CMTST (scalar)
D5.16 DUP (scalar, element)
D5.17 FABD (scalar)
D5.18 FACGE (scalar)
D5.19 FACGT (scalar)
D5.20 FADDP (scalar)
D5.21 FCMEQ (scalar, register)
D5.22 FCMEQ (scalar, zero)
D5.23 FCMGE (scalar, register)
D5.24 FCMGE (scalar, zero)
D5.25 FCMGT (scalar, register)
D5.26 FCMGT (scalar, zero)
D5.27 FCMLA (scalar, by element)
D5.28 FCMLE (scalar, zero)
D5.29 FCMLT (scalar, zero)
D5.30 FCVTAS (scalar)
D5.31 FCVTAU (scalar)
D5.32 FCVTMS (scalar)
D5.33 FCVTMU (scalar)
D5.34 FCVTNS (scalar)
D5.35 FCVTNU (scalar)
D5.36 FCVTPS (scalar)
D5.37 FCVTPU (scalar)
D5.38 FCVTXN (scalar)
D5.39 FCVTZS (scalar, fixed-point)
D5.40 FCVTZS (scalar, integer)
D5.41 FCVTZU (scalar, fixed-point)
D5.42 FCVTZU (scalar, integer)
D5.43 FMAXNMP (scalar)
D5.44 FMAXP (scalar)
D5.45 FMINNMP (scalar)
D5.46 FMINP (scalar)
D5.47 FMLA (scalar, by element)
D5.48 FMLAL, (scalar, by element)
D5.49 FMLS (scalar, by element)
D5.50 FMLSL, (scalar, by element)
D5.51 FMUL (scalar, by element)
D5.52 FMULX (scalar, by element)
D5.53 FMULX (scalar)
D5.54 FRECPE (scalar)
D5.55 FRECPS (scalar)
D5.56 FRSQRTE (scalar)
D5.57 FRSQRTS (scalar)
D5.58 MOV (scalar)
D5.59 NEG (scalar)
D5.60 SCVTF (scalar, fixed-point)
D5.61 SCVTF (scalar, integer)
D5.62 SHL (scalar)
D5.63 SLI (scalar)
D5.64 SQABS (scalar)
D5.65 SQADD (scalar)
D5.66 SQDMLAL (scalar, by element)
D5.67 SQDMLAL (scalar)
D5.68 SQDMLSL (scalar, by element)
D5.69 SQDMLSL (scalar)
D5.70 SQDMULH (scalar, by element)
D5.71 SQDMULH (scalar)
D5.72 SQDMULL (scalar, by element)
D5.73 SQDMULL (scalar)
D5.74 SQNEG (scalar)
D5.75 SQRDMLAH (scalar, by element)
D5.76 SQRDMLAH (scalar)
D5.77 SQRDMLSH (scalar, by element)
D5.78 SQRDMLSH (scalar)
D5.79 SQRDMULH (scalar, by element)
D5.80 SQRDMULH (scalar)
D5.81 SQRSHL (scalar)
D5.82 SQRSHRN (scalar)
D5.83 SQRSHRUN (scalar)
D5.84 SQSHL (scalar, immediate)
D5.85 SQSHL (scalar, register)
D5.86 SQSHLU (scalar)
D5.87 SQSHRN (scalar)
D5.88 SQSHRUN (scalar)
D5.89 SQSUB (scalar)
D5.90 SQXTN (scalar)
D5.91 SQXTUN (scalar)
D5.92 SRI (scalar)
D5.93 SRSHL (scalar)
D5.94 SRSHR (scalar)
D5.95 SRSRA (scalar)
D5.96 SSHL (scalar)
D5.97 SSHR (scalar)
D5.98 SSRA (scalar)
D5.99 SUB (scalar)
D5.100 SUQADD (scalar)
D5.101 UCVTF (scalar, fixed-point)
D5.102 UCVTF (scalar, integer)
D5.103 UQADD (scalar)
D5.104 UQRSHL (scalar)
D5.105 UQRSHRN (scalar)
D5.106 UQSHL (scalar, immediate)
D5.107 UQSHL (scalar, register)
D5.108 UQSHRN (scalar)
D5.109 UQSUB (scalar)
D5.110 UQXTN (scalar)
D5.111 URSHL (scalar)
D5.112 URSHR (scalar)
D5.113 URSRA (scalar)
D5.114 USHL (scalar)
D5.115 USHR (scalar)
D5.116 USQADD (scalar)
D5.117 USRA (scalar)
D6 A64 SIMD Vector Instructions
D6.1 A64 SIMD Vector instructions in alphabetical order
D6.2 ABS (vector)
D6.3 ADD (vector)
D6.4 ADDHN, ADDHN2 (vector)
D6.5 ADDP (vector)
D6.6 ADDV (vector)
D6.7 AND (vector)
D6.8 BIC (vector, immediate)
D6.9 BIC (vector, register)
D6.10 BIF (vector)
D6.11 BIT (vector)
D6.12 BSL (vector)
D6.13 CLS (vector)
D6.14 CLZ (vector)
D6.15 CMEQ (vector, register)
D6.16 CMEQ (vector, zero)
D6.17 CMGE (vector, register)
D6.18 CMGE (vector, zero)
D6.19 CMGT (vector, register)
D6.20 CMGT (vector, zero)
D6.21 CMHI (vector, register)
D6.22 CMHS (vector, register)
D6.23 CMLE (vector, zero)
D6.24 CMLT (vector, zero)
D6.25 CMTST (vector)
D6.26 CNT (vector)
D6.27 DUP (vector, element)
D6.28 DUP (vector, general)
D6.29 EOR (vector)
D6.30 EXT (vector)
D6.31 FABD (vector)
D6.32 FABS (vector)
D6.33 FACGE (vector)
D6.34 FACGT (vector)
D6.35 FADD (vector)
D6.36 FADDP (vector)
D6.37 FCADD (vector)
D6.38 FCMEQ (vector, register)
D6.39 FCMEQ (vector, zero)
D6.40 FCMGE (vector, register)
D6.41 FCMGE (vector, zero)
D6.42 FCMGT (vector, register)
D6.43 FCMGT (vector, zero)
D6.44 FCMLA (vector)
D6.45 FCMLE (vector, zero)
D6.46 FCMLT (vector, zero)
D6.47 FCVTAS (vector)
D6.48 FCVTAU (vector)
D6.49 FCVTL, FCVTL2 (vector)
D6.50 FCVTMS (vector)
D6.51 FCVTMU (vector)
D6.52 FCVTN, FCVTN2 (vector)
D6.53 FCVTNS (vector)
D6.54 FCVTNU (vector)
D6.55 FCVTPS (vector)
D6.56 FCVTPU (vector)
D6.57 FCVTXN, FCVTXN2 (vector)
D6.58 FCVTZS (vector, fixed-point)
D6.59 FCVTZS (vector, integer)
D6.60 FCVTZU (vector, fixed-point)
D6.61 FCVTZU (vector, integer)
D6.62 FDIV (vector)
D6.63 FMAX (vector)
D6.64 FMAXNM (vector)
D6.65 FMAXNMP (vector)
D6.66 FMAXNMV (vector)
D6.67 FMAXP (vector)
D6.68 FMAXV (vector)
D6.69 FMIN (vector)
D6.70 FMINNM (vector)
D6.71 FMINNMP (vector)
D6.72 FMINNMV (vector)
D6.73 FMINP (vector)
D6.74 FMINV (vector)
D6.75 FMLA (vector, by element)
D6.76 FMLA (vector)
D6.77 FMLAL, (vector)
D6.78 FMLS (vector, by element)
D6.79 FMLS (vector)
D6.80 FMLSL, (vector)
D6.81 FMOV (vector, immediate)
D6.82 FMUL (vector, by element)
D6.83 FMUL (vector)
D6.84 FMULX (vector, by element)
D6.85 FMULX (vector)
D6.86 FNEG (vector)
D6.87 FRECPE (vector)
D6.88 FRECPS (vector)
D6.89 FRECPX (vector)
D6.90 FRINTA (vector)
D6.91 FRINTI (vector)
D6.92 FRINTM (vector)
D6.93 FRINTN (vector)
D6.94 FRINTP (vector)
D6.95 FRINTX (vector)
D6.96 FRINTZ (vector)
D6.97 FRSQRTE (vector)
D6.98 FRSQRTS (vector)
D6.99 FSQRT (vector)
D6.100 FSUB (vector)
D6.101 INS (vector, element)
D6.102 INS (vector, general)
D6.103 LD1 (vector, multiple structures)
D6.104 LD1 (vector, single structure)
D6.105 LD1R (vector)
D6.106 LD2 (vector, multiple structures)
D6.107 LD2 (vector, single structure)
D6.108 LD2R (vector)
D6.109 LD3 (vector, multiple structures)
D6.110 LD3 (vector, single structure)
D6.111 LD3R (vector)
D6.112 LD4 (vector, multiple structures)
D6.113 LD4 (vector, single structure)
D6.114 LD4R (vector)
D6.115 MLA (vector, by element)
D6.116 MLA (vector)
D6.117 MLS (vector, by element)
D6.118 MLS (vector)
D6.119 MOV (vector, element)
D6.120 MOV (vector, from general)
D6.121 MOV (vector)
D6.122 MOV (vector, to general)
D6.123 MOVI (vector)
D6.124 MUL (vector, by element)
D6.125 MUL (vector)
D6.126 MVN (vector)
D6.127 MVNI (vector)
D6.128 NEG (vector)
D6.129 NOT (vector)
D6.130 ORN (vector)
D6.131 ORR (vector, immediate)
D6.132 ORR (vector, register)
D6.133 PMUL (vector)
D6.134 PMULL, PMULL2 (vector)
D6.135 RADDHN, RADDHN2 (vector)
D6.136 RBIT (vector)
D6.137 REV16 (vector)
D6.138 REV32 (vector)
D6.139 REV64 (vector)
D6.140 RSHRN, RSHRN2 (vector)
D6.141 RSUBHN, RSUBHN2 (vector)
D6.142 SABA (vector)
D6.143 SABAL, SABAL2 (vector)
D6.144 SABD (vector)
D6.145 SABDL, SABDL2 (vector)
D6.146 SADALP (vector)
D6.147 SADDL, SADDL2 (vector)
D6.148 SADDLP (vector)
D6.149 SADDLV (vector)
D6.150 SADDW, SADDW2 (vector)
D6.151 SCVTF (vector, fixed-point)
D6.152 SCVTF (vector, integer)
D6.153 SDOT (vector, by element)
D6.154 SDOT (vector)
D6.155 SHADD (vector)
D6.156 SHL (vector)
D6.157 SHLL, SHLL2 (vector)
D6.158 SHRN, SHRN2 (vector)
D6.159 SHSUB (vector)
D6.160 SLI (vector)
D6.161 SMAX (vector)
D6.162 SMAXP (vector)
D6.163 SMAXV (vector)
D6.164 SMIN (vector)
D6.165 SMINP (vector)
D6.166 SMINV (vector)
D6.167 SMLAL, SMLAL2 (vector, by element)
D6.168 SMLAL, SMLAL2 (vector)
D6.169 SMLSL, SMLSL2 (vector, by element)
D6.170 SMLSL, SMLSL2 (vector)
D6.171 SMOV (vector)
D6.172 SMULL, SMULL2 (vector, by element)
D6.173 SMULL, SMULL2 (vector)
D6.174 SQABS (vector)
D6.175 SQADD (vector)
D6.176 SQDMLAL, SQDMLAL2 (vector, by element)
D6.177 SQDMLAL, SQDMLAL2 (vector)
D6.178 SQDMLSL, SQDMLSL2 (vector, by element)
D6.179 SQDMLSL, SQDMLSL2 (vector)
D6.180 SQDMULH (vector, by element)
D6.181 SQDMULH (vector)
D6.182 SQDMULL, SQDMULL2 (vector, by element)
D6.183 SQDMULL, SQDMULL2 (vector)
D6.184 SQNEG (vector)
D6.185 SQRDMLAH (vector, by element)
D6.186 SQRDMLAH (vector)
D6.187 SQRDMLSH (vector, by element)
D6.188 SQRDMLSH (vector)
D6.189 SQRDMULH (vector, by element)
D6.190 SQRDMULH (vector)
D6.191 SQRSHL (vector)
D6.192 SQRSHRN, SQRSHRN2 (vector)
D6.193 SQRSHRUN, SQRSHRUN2 (vector)
D6.194 SQSHL (vector, immediate)
D6.195 SQSHL (vector, register)
D6.196 SQSHLU (vector)
D6.197 SQSHRN, SQSHRN2 (vector)
D6.198 SQSHRUN, SQSHRUN2 (vector)
D6.199 SQSUB (vector)
D6.200 SQXTN, SQXTN2 (vector)
D6.201 SQXTUN, SQXTUN2 (vector)
D6.202 SRHADD (vector)
D6.203 SRI (vector)
D6.204 SRSHL (vector)
D6.205 SRSHR (vector)
D6.206 SRSRA (vector)
D6.207 SSHL (vector)
D6.208 SSHLL, SSHLL2 (vector)
D6.209 SSHR (vector)
D6.210 SSRA (vector)
D6.211 SSUBL, SSUBL2 (vector)
D6.212 SSUBW, SSUBW2 (vector)
D6.213 ST1 (vector, multiple structures)
D6.214 ST1 (vector, single structure)
D6.215 ST2 (vector, multiple structures)
D6.216 ST2 (vector, single structure)
D6.217 ST3 (vector, multiple structures)
D6.218 ST3 (vector, single structure)
D6.219 ST4 (vector, multiple structures)
D6.220 ST4 (vector, single structure)
D6.221 SUB (vector)
D6.222 SUBHN, SUBHN2 (vector)
D6.223 SUQADD (vector)
D6.224 SXTL, SXTL2 (vector)
D6.225 TBL (vector)
D6.226 TBX (vector)
D6.227 TRN1 (vector)
D6.228 TRN2 (vector)
D6.229 UABA (vector)
D6.230 UABAL, UABAL2 (vector)
D6.231 UABD (vector)
D6.232 UABDL, UABDL2 (vector)
D6.233 UADALP (vector)
D6.234 UADDL, UADDL2 (vector)
D6.235 UADDLP (vector)
D6.236 UADDLV (vector)
D6.237 UADDW, UADDW2 (vector)
D6.238 UCVTF (vector, fixed-point)
D6.239 UCVTF (vector, integer)
D6.240 UDOT (vector, by element)
D6.241 UDOT (vector)
D6.242 UHADD (vector)
D6.243 UHSUB (vector)
D6.244 UMAX (vector)
D6.245 UMAXP (vector)
D6.246 UMAXV (vector)
D6.247 UMIN (vector)
D6.248 UMINP (vector)
D6.249 UMINV (vector)
D6.250 UMLAL, UMLAL2 (vector, by element)
D6.251 UMLAL, UMLAL2 (vector)
D6.252 UMLSL, UMLSL2 (vector, by element)
D6.253 UMLSL, UMLSL2 (vector)
D6.254 UMOV (vector)
D6.255 UMULL, UMULL2 (vector, by element)
D6.256 UMULL, UMULL2 (vector)
D6.257 UQADD (vector)
D6.258 UQRSHL (vector)
D6.259 UQRSHRN, UQRSHRN2 (vector)
D6.260 UQSHL (vector, immediate)
D6.261 UQSHL (vector, register)
D6.262 UQSHRN, UQSHRN2 (vector)
D6.263 UQSUB (vector)
D6.264 UQXTN, UQXTN2 (vector)
D6.265 URECPE (vector)
D6.266 URHADD (vector)
D6.267 URSHL (vector)
D6.268 URSHR (vector)
D6.269 URSQRTE (vector)
D6.270 URSRA (vector)
D6.271 USHL (vector)
D6.272 USHLL, USHLL2 (vector)
D6.273 USHR (vector)
D6.274 USQADD (vector)
D6.275 USRA (vector)
D6.276 USUBL, USUBL2 (vector)
D6.277 USUBW, USUBW2 (vector)
D6.278 UXTL, UXTL2 (vector)
D6.279 UZP1 (vector)
D6.280 UZP2 (vector)
D6.281 XTN, XTN2 (vector)
D6.282 ZIP1 (vector)
D6.283 ZIP2 (vector)
D7 A64 Cryptographic Algorithms
D7.1 A64 Cryptographic instructions

List of Figures

A2-1 Organization of general-purpose registers and Program Status Registers
B1-1 Extension register bank for Advanced SIMD in AArch32 state
B1-2 Extension register bank for Advanced SIMD in AArch64 state
B2-1 Extension register bank for floating-point in AArch32 state
B2-2 Extension register bank for floating-point in AArch64 state
C2-1 ASR #3
C2-2 LSR #3
C2-3 LSL #3
C2-4 ROR #3
C2-5 RRX
C3-1 De-interleaving an array of 3-element structures
C3-2 Operation of doubleword VEXT for imm = 3
C3-3 Example of operation of VPADAL (in this case for data type S16)
C3-4 Example of operation of VPADD (in this case, for data type I16)
C3-5 Example of operation of doubleword VPADDL (in this case, for data type S16)
C3-6 Operation of quadword VSHL.I64 Qd, Qm, #1
C3-7 Operation of quadword VSLI.64 Qd, Qm, #1
C3-8 Operation of doubleword VSRI.64 Dd, Dm, #2
C3-9 Operation of doubleword VTRN.8
C3-10 Operation of doubleword VTRN.32

List of Tables

A2-1 AArch32 processor modes
A2-2 Predeclared core registers in AArch32 state
A2-3 Predeclared extension registers in AArch32 state
A2-4 A32 instruction groups
A3-1 Predeclared core registers in AArch64 state
A3-2 Predeclared extension registers in AArch64 state
A3-3 A64 instruction groups
B1-1 Differences in syntax and mnemonics between A32/T32 and A64 Advanced SIMD instructions
B1-2 Advanced SIMD data types
B1-3 Advanced SIMD saturation ranges
B2-1 Differences in syntax and mnemonics between A32/T32 and A64 floating-point instructions
C1-1 Condition code suffixes
C1-2 Condition code suffixes and related flags
C1-3 Condition codes
C1-4 Conditional branches only
C1-5 All instructions conditional
C2-1 Summary of instructions
C2-2 PC-relative offsets
C2-3 Register-relative offsets
C2-4 B instruction availability and range
C2-5 BL instruction availability and range
C2-6 BLX instruction availability and range
C2-7 BX instruction availability and range
C2-8 BXJ instruction availability and range
C2-9 Permitted instructions inside an IT block
C2-10 Offsets and architectures, LDR, word, halfword, and byte
C2-11 PC-relative offsets
C2-12 Options and architectures, LDR (register offsets)
C2-13 Register-relative offsets
C2-14 Offsets and architectures, LDR (User mode)
C2-15 Offsets and architectures, STR, word, halfword, and byte
C2-16 Options and architectures, STR (register offsets)
C2-17 Offsets and architectures, STR (User mode)
C3-1 Summary of Advanced SIMD instructions
C3-2 Summary of shared Advanced SIMD and floating-point instructions
C3-3 Patterns for immediate value in VBIC (immediate)
C3-4 Permitted combinations of parameters for VLDn (single n-element structure to one lane)
C3-5 Permitted combinations of parameters for VLDn (single n-element structure to all lanes)
C3-6 Permitted combinations of parameters for VLDn (multiple n-element structures)
C3-7 Available immediate values in VMOV (immediate)
C3-8 Available immediate values in VMVN (immediate)
C3-9 Patterns for immediate value in VORR (immediate)
C3-10 Available immediate ranges in VQRSHRN and VQRSHRUN (by immediate)
C3-11 Available immediate ranges in VQSHL and VQSHLU (by immediate)
C3-12 Available immediate ranges in VQSHRN and VQSHRUN (by immediate)
C3-13 Results for out-of-range inputs in VRECPE
C3-14 Results for out-of-range inputs in VRECPS
C3-15 Available immediate ranges in VRSHR (by immediate)
C3-16 Available immediate ranges in VRSHRN (by immediate)
C3-17 Results for out-of-range inputs in VRSQRTE
C3-18 Results for out-of-range inputs in VRSQRTS
C3-19 Available immediate ranges in VRSRA (by immediate)
C3-20 Available immediate ranges in VSHL (by immediate)
C3-21 Available immediate ranges in VSHLL (by immediate)
C3-22 Available immediate ranges in VSHR (by immediate)
C3-23 Available immediate ranges in VSHRN (by immediate)
C3-24 Available immediate ranges in VSRA (by immediate)
C3-25 Permitted combinations of parameters for VSTn (multiple n-element structures)
C3-26 Permitted combinations of parameters for VSTn (single n-element structure to one lane)
C3-27 Operation of doubleword VUZP.8
C3-28 Operation of quadword VUZP.32
C3-29 Operation of doubleword VZIP.8
C3-30 Operation of quadword VZIP.32
C4-1 Summary of floating-point instructions
C5-1 Summary of A32/T32 cryptographic instructions
D1-1 Condition code suffixes
D1-2 Condition code suffixes and related flags
D2-1 Summary of A64 general instructions
D2-2 ADD (64-bit general registers) specifier combinations
D2-3 ADDS (64-bit general registers) specifier combinations
D2-4 SYS parameter values corresponding to AT operations
D2-5 CMN (64-bit general registers) specifier combinations
D2-6 CMP (64-bit general registers) specifier combinations
D2-7 SYS parameter values corresponding to DC operations
D2-8 SYS parameter values corresponding to IC operations
D2-9 SUB (64-bit general registers) specifier combinations
D2-10 SUBS (64-bit general registers) specifier combinations
D2-11 SYS parameter values corresponding to TLBI operations
D3-1 Summary of A64 data transfer instructions
D4-1 Summary of A64 floating-point instructions
D5-1 Summary of A64 SIMD scalar instructions
D5-2 DUP (Scalar) specifier combinations
D5-3 FCMLA (Scalar) specifier combinations
D5-4 FCVTZS (Scalar) specifier combinations
D5-5 FCVTZU (Scalar) specifier combinations
D5-6 FMLA (Scalar, single-precision and double-precision) specifier combinations
D5-7 FMLS (Scalar, single-precision and double-precision) specifier combinations
D5-8 FMUL (Scalar, single-precision and double-precision) specifier combinations
D5-9 FMULX (Scalar, single-precision and double-precision) specifier combinations
D5-10 MOV (Scalar) specifier combinations
D5-11 SCVTF (Scalar) specifier combinations
D5-12 SQDMLAL (Scalar) specifier combinations
D5-13 SQDMLAL (Scalar) specifier combinations
D5-14 SQDMLSL (Scalar) specifier combinations
D5-15 SQDMLSL (Scalar) specifier combinations
D5-16 SQDMULH (Scalar) specifier combinations
D5-17 SQDMULL (Scalar) specifier combinations
D5-18 SQDMULL (Scalar) specifier combinations
D5-19 SQRDMLAH (Scalar) specifier combinations
D5-20 SQRDMLSH (Scalar) specifier combinations
D5-21 SQRDMULH (Scalar) specifier combinations
D5-22 SQRSHRN (Scalar) specifier combinations
D5-23 SQRSHRUN (Scalar) specifier combinations
D5-24 SQSHL (Scalar) specifier combinations
D5-25 SQSHLU (Scalar) specifier combinations
D5-26 SQSHRN (Scalar) specifier combinations
D5-27 SQSHRUN (Scalar) specifier combinations
D5-28 SQXTN (Scalar) specifier combinations
D5-29 SQXTUN (Scalar) specifier combinations
D5-30 UCVTF (Scalar) specifier combinations
D5-31 UQRSHRN (Scalar) specifier combinations
D5-32 UQSHL (Scalar) specifier combinations
D5-33 UQSHRN (Scalar) specifier combinations
D5-34 UQXTN (Scalar) specifier combinations
D6-1 Summary of A64 SIMD Vector instructions
D6-2 ADDHN, ADDHN2 (Vector) specifier combinations
D6-3 ADDV (Vector) specifier combinations
D6-4 DUP (Vector) specifier combinations
D6-5 DUP (Vector) specifier combinations
D6-6 EXT (Vector) specifier combinations
D6-7 FCVTL, FCVTL2 (Vector) specifier combinations
D6-8 FCVTN, FCVTN2 (Vector) specifier combinations
D6-9 FCVTXN{2} (Vector) specifier combinations
D6-10 FCVTZS (Vector) specifier combinations
D6-11 FCVTZU (Vector) specifier combinations
D6-12 FMLA (Vector, single-precision and double-precision) specifier combinations
D6-13 FMLS (Vector, single-precision and double-precision) specifier combinations
D6-14 FMUL (Vector, single-precision and double-precision) specifier combinations
D6-15 FMULX (Vector, single-precision and double-precision) specifier combinations
D6-16 INS (Vector) specifier combinations
D6-17 INS (Vector) specifier combinations
D6-18 LD1 (One register, immediate offset) specifier combinations
D6-19 LD1 (Two registers, immediate offset) specifier combinations
D6-20 LD1 (Three registers, immediate offset) specifier combinations
D6-21 LD1 (Four registers, immediate offset) specifier combinations
D6-22 LD1R (Immediate offset) specifier combinations
D6-23 LD2R (Immediate offset) specifier combinations
D6-24 LD3R (Immediate offset) specifier combinations
D6-25 LD4R (Immediate offset) specifier combinations
D6-26 MLA (Vector) specifier combinations
D6-27 MLS (Vector) specifier combinations
D6-28 MOV (Vector) specifier combinations
D6-29 MOV (Vector) specifier combinations
D6-30 MUL (Vector) specifier combinations
D6-31 PMULL, PMULL2 (Vector) specifier combinations
D6-32 RADDHN, RADDHN2 (Vector) specifier combinations
D6-33 RSHRN, RSHRN2 (Vector) specifier combinations
D6-34 RSUBHN, RSUBHN2 (Vector) specifier combinations
D6-35 SABAL, SABAL2 (Vector) specifier combinations
D6-36 SABDL, SABDL2 (Vector) specifier combinations
D6-37 SADALP (Vector) specifier combinations
D6-38 SADDL, SADDL2 (Vector) specifier combinations
D6-39 SADDLP (Vector) specifier combinations
D6-40 SADDLV (Vector) specifier combinations
D6-41 SADDW, SADDW2 (Vector) specifier combinations
D6-42 SCVTF (Vector) specifier combinations
D6-43 SHL (Vector) specifier combinations
D6-44 SHLL, SHLL2 (Vector) specifier combinations
D6-45 SHRN, SHRN2 (Vector) specifier combinations
D6-46 SLI (Vector) specifier combinations
D6-47 SMAXV (Vector) specifier combinations
D6-48 SMINV (Vector) specifier combinations
D6-49 SMLAL, SMLAL2 (Vector) specifier combinations
D6-50 SMLAL, SMLAL2 (Vector) specifier combinations
D6-51 SMLSL, SMLSL2 (Vector) specifier combinations
D6-52 SMLSL, SMLSL2 (Vector) specifier combinations
D6-53 SMOV (32-bit) specifier combinations
D6-54 SMOV (64-bit) specifier combinations
D6-55 SMULL, SMULL2 (Vector) specifier combinations
D6-56 SMULL, SMULL2 (Vector) specifier combinations
D6-57 SQDMLAL{2} (Vector) specifier combinations
D6-58 SQDMLAL{2} (Vector) specifier combinations
D6-59 SQDMLSL{2} (Vector) specifier combinations
D6-60 SQDMLSL{2} (Vector) specifier combinations
D6-61 SQDMULH (Vector) specifier combinations
D6-62 SQDMULL{2} (Vector) specifier combinations
D6-63 SQDMULL{2} (Vector) specifier combinations
D6-64 SQRDMLAH (Vector) specifier combinations
D6-65 SQRDMLSH (Vector) specifier combinations
D6-66 SQRDMULH (Vector) specifier combinations
D6-67 SQRSHRN{2} (Vector) specifier combinations
D6-68 SQRSHRUN{2} (Vector) specifier combinations
D6-69 SQSHL (Vector) specifier combinations
D6-70 SQSHLU (Vector) specifier combinations
D6-71 SQSHRN{2} (Vector) specifier combinations
D6-72 SQSHRUN{2} (Vector) specifier combinations
D6-73 SQXTN{2} (Vector) specifier combinations
D6-74 SQXTUN{2} (Vector) specifier combinations
D6-75 SRI (Vector) specifier combinations
D6-76 SRSHR (Vector) specifier combinations
D6-77 SRSRA (Vector) specifier combinations
D6-78 SSHLL, SSHLL2 (Vector) specifier combinations
D6-79 SSHR (Vector) specifier combinations
D6-80 SSRA (Vector) specifier combinations
D6-81 SSUBL, SSUBL2 (Vector) specifier combinations
D6-82 SSUBW, SSUBW2 (Vector) specifier combinations
D6-83 ST1 (One register, immediate offset) specifier combinations
D6-84 ST1 (Two registers, immediate offset) specifier combinations
D6-85 ST1 (Three registers, immediate offset) specifier combinations
D6-86 ST1 (Four registers, immediate offset) specifier combinations
D6-87 SUBHN, SUBHN2 (Vector) specifier combinations
D6-88 SXTL, SXTL2 (Vector) specifier combinations
D6-89 UABAL, UABAL2 (Vector) specifier combinations
D6-90 UABDL, UABDL2 (Vector) specifier combinations
D6-91 UADALP (Vector) specifier combinations
D6-92 UADDL, UADDL2 (Vector) specifier combinations
D6-93 UADDLP (Vector) specifier combinations
D6-94 UADDLV (Vector) specifier combinations
D6-95 UADDW, UADDW2 (Vector) specifier combinations
D6-96 UCVTF (Vector) specifier combinations
D6-97 UMAXV (Vector) specifier combinations
D6-98 UMINV (Vector) specifier combinations
D6-99 UMLAL, UMLAL2 (Vector) specifier combinations
D6-100 UMLAL, UMLAL2 (Vector) specifier combinations
D6-101 UMLSL, UMLSL2 (Vector) specifier combinations
D6-102 UMLSL, UMLSL2 (Vector) specifier combinations
D6-103 UMOV (32-bit) specifier combinations
D6-104 UMULL, UMULL2 (Vector) specifier combinations
D6-105 UMULL, UMULL2 (Vector) specifier combinations
D6-106 UQRSHRN{2} (Vector) specifier combinations
D6-107 UQSHL (Vector) specifier combinations
D6-108 UQSHRN{2} (Vector) specifier combinations
D6-109 UQXTN{2} (Vector) specifier combinations
D6-110 URSHR (Vector) specifier combinations
D6-111 URSRA (Vector) specifier combinations
D6-112 USHLL, USHLL2 (Vector) specifier combinations
D6-113 USHR (Vector) specifier combinations
D6-114 USRA (Vector) specifier combinations
D6-115 USUBL, USUBL2 (Vector) specifier combinations
D6-116 USUBW, USUBW2 (Vector) specifier combinations
D6-117 UXTL, UXTL2 (Vector) specifier combinations
D6-118 XTN, XTN2 (Vector) specifier combinations
D7-1 Summary of A64 cryptographic instructions

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0100-00 25 October 2018 Non-Confidential First Release

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