Instruction Set Assembly Guide for Armv7 and earlier Arm® architectures Reference Guide

Version 2.0


Table of Contents

Preface
About this book
Using this book
Glossary
Typographic conventions
Feedback
Feedback on this product
Feedback on content
Other information
Part A Instruction Set Overview
A1 Overview of AArch32 state
A1.1 Terminology
A1.2 Changing between A32 and T32 instruction set states
A1.3 Processor modes, and privileged and unprivileged software execution
A1.4 Processor modes in Armv6‑M, Armv7‑M, and Armv8‑M
A1.5 Registers in AArch32 state
A1.6 General-purpose registers in AArch32 state
A1.7 Register accesses in AArch32 state
A1.8 Predeclared core register names in AArch32 state
A1.9 Predeclared extension register names in AArch32 state
A1.10 Program Counter in AArch32 state
A1.11 The Q flag in AArch32 state
A1.12 Application Program Status Register
A1.13 Current Program Status Register in AArch32 state
A1.14 Saved Program Status Registers in AArch32 state
A1.15 A32 and T32 instruction set overview
A1.16 Access to the inline barrel shifter in AArch32 state
Part B Advanced SIMD and Floating-point Programming
B1 Advanced SIMD Programming
B1.1 Architecture support for Advanced SIMD
B1.2 Extension register bank mapping for Advanced SIMD in AArch32 state
B1.3 Views of the Advanced SIMD register bank in AArch32 state
B1.4 Load values to Advanced SIMD registers
B1.5 Conditional execution of A32/T32 Advanced SIMD instructions
B1.6 Floating-point exceptions for Advanced SIMD in A32/T32 instructions
B1.7 Advanced SIMD data types in A32/T32 instructions
B1.8 Polynomial arithmetic over {0,1}
B1.9 Advanced SIMD vectors
B1.10 Normal, long, wide, and narrow Advanced SIMD instructions
B1.11 Saturating Advanced SIMD instructions
B1.12 Advanced SIMD scalars
B1.13 Extended notation extension for Advanced SIMD
B1.14 Advanced SIMD system registers in AArch32 state
B1.15 Flush-to-zero mode in Advanced SIMD
B1.16 When to use flush-to-zero mode in Advanced SIMD
B1.17 The effects of using flush-to-zero mode in Advanced SIMD
B1.18 Advanced SIMD operations not affected by flush-to-zero mode
B2 Floating-point Programming
B2.1 Architecture support for floating-point
B2.2 Extension register bank mapping for floating-point in AArch32 state
B2.3 Views of the floating-point extension register bank in AArch32 state
B2.4 Load values to floating-point registers
B2.5 Conditional execution of A32/T32 floating-point instructions
B2.6 Floating-point exceptions for floating-point in A32/T32 instructions
B2.7 Floating-point data types in A32/T32 instructions
B2.8 Extended notation extension for floating-point code
B2.9 Floating-point system registers in AArch32 state
B2.10 Flush-to-zero mode in floating-point
B2.11 When to use flush-to-zero mode in floating-point
B2.12 The effects of using flush-to-zero mode in floating-point
B2.13 Floating-point operations not affected by flush-to-zero mode
Part C A32/T32 Instruction Set Reference
C1 Condition Codes
C1.1 Conditional instructions
C1.2 Conditional execution in A32 code
C1.3 Conditional execution in T32 code
C1.4 Condition flags
C1.5 Updates to the condition flags in A32/T32 code
C1.6 Floating-point instructions that update the condition flags
C1.7 Carry flag
C1.8 Overflow flag
C1.9 Condition code suffixes
C1.10 Condition code suffixes and related flags
C1.11 Comparison of condition code meanings in integer and floating-point code
C1.12 Benefits of using conditional execution in A32 and T32 code
C1.13 Example showing the benefits of conditional instructions in A32 and T32 code
C1.14 Optimization for execution speed
C2 A32 and T32 Instructions
C2.1 A32 and T32 instruction summary
C2.2 Instruction width specifiers
C2.3 Flexible second operand (Operand2)
C2.4 Syntax of Operand2 as a constant
C2.5 Syntax of Operand2 as a register with optional shift
C2.6 Shift operations
C2.7 Saturating instructions
C2.8 ADC
C2.9 ADD
C2.10 ADR (PC-relative)
C2.11 ADR (register-relative)
C2.12 AND
C2.13 ASR
C2.14 B
C2.15 BFC
C2.16 BFI
C2.17 BIC
C2.18 BKPT
C2.19 BL
C2.20 BLX, BLXNS
C2.21 BX, BXNS
C2.22 BXJ
C2.23 CBZ and CBNZ
C2.24 CDP and CDP2
C2.25 CLREX
C2.26 CLZ
C2.27 CMP and CMN
C2.28 CPS
C2.29 CRC32
C2.30 CRC32C
C2.31 CSDB
C2.32 DBG
C2.33 DMB
C2.34 DSB
C2.35 EOR
C2.36 ERET
C2.37 ESB
C2.38 HLT
C2.39 HVC
C2.40 ISB
C2.41 IT
C2.42 LDA
C2.43 LDAEX
C2.44 LDC and LDC2
C2.45 LDM
C2.46 LDR (immediate offset)
C2.47 LDR (PC-relative)
C2.48 LDR (register offset)
C2.49 LDR (register-relative)
C2.50 LDR, unprivileged
C2.51 LDREX
C2.52 LSL
C2.53 LSR
C2.54 MCR and MCR2
C2.55 MCRR and MCRR2
C2.56 MLA
C2.57 MLS
C2.58 MOV
C2.59 MOVT
C2.60 MRC and MRC2
C2.61 MRRC and MRRC2
C2.62 MRS (PSR to general-purpose register)
C2.63 MRS (system coprocessor register to general-purpose register)
C2.64 MSR (general-purpose register to system coprocessor register)
C2.65 MSR (general-purpose register to PSR)
C2.66 MUL
C2.67 MVN
C2.68 NOP
C2.69 ORN (T32 only)
C2.70 ORR
C2.71 PKHBT and PKHTB
C2.72 PLD, PLDW, and PLI
C2.73 POP
C2.74 PUSH
C2.75 QADD
C2.76 QADD8
C2.77 QADD16
C2.78 QASX
C2.79 QDADD
C2.80 QDSUB
C2.81 QSAX
C2.82 QSUB
C2.83 QSUB8
C2.84 QSUB16
C2.85 RBIT
C2.86 REV
C2.87 REV16
C2.88 REVSH
C2.89 RFE
C2.90 ROR
C2.91 RRX
C2.92 RSB
C2.93 RSC
C2.94 SADD8
C2.95 SADD16
C2.96 SASX
C2.97 SBC
C2.98 SBFX
C2.99 SDIV
C2.100 SEL
C2.101 SETEND
C2.102 SETPAN
C2.103 SEV
C2.104 SEVL
C2.105 SG
C2.106 SHADD8
C2.107 SHADD16
C2.108 SHASX
C2.109 SHSAX
C2.110 SHSUB8
C2.111 SHSUB16
C2.112 SMC
C2.113 SMLAxy
C2.114 SMLAD
C2.115 SMLAL
C2.116 SMLALD
C2.117 SMLALxy
C2.118 SMLAWy
C2.119 SMLSD
C2.120 SMLSLD
C2.121 SMMLA
C2.122 SMMLS
C2.123 SMMUL
C2.124 SMUAD
C2.125 SMULxy
C2.126 SMULL
C2.127 SMULWy
C2.128 SMUSD
C2.129 SRS
C2.130 SSAT
C2.131 SSAT16
C2.132 SSAX
C2.133 SSUB8
C2.134 SSUB16
C2.135 STC and STC2
C2.136 STL
C2.137 STLEX
C2.138 STM
C2.139 STR (immediate offset)
C2.140 STR (register offset)
C2.141 STR, unprivileged
C2.142 STREX
C2.143 SUB
C2.144 SUBS pc, lr
C2.145 SVC
C2.146 SWP and SWPB
C2.147 SXTAB
C2.148 SXTAB16
C2.149 SXTAH
C2.150 SXTB
C2.151 SXTB16
C2.152 SXTH
C2.153 SYS
C2.154 TBB and TBH
C2.155 TEQ
C2.156 TST
C2.157 TT, TTT, TTA, TTAT
C2.158 UADD8
C2.159 UADD16
C2.160 UASX
C2.161 UBFX
C2.162 UDF
C2.163 UDIV
C2.164 UHADD8
C2.165 UHADD16
C2.166 UHASX
C2.167 UHSAX
C2.168 UHSUB8
C2.169 UHSUB16
C2.170 UMAAL
C2.171 UMLAL
C2.172 UMULL
C2.173 UQADD8
C2.174 UQADD16
C2.175 UQASX
C2.176 UQSAX
C2.177 UQSUB8
C2.178 UQSUB16
C2.179 USAD8
C2.180 USADA8
C2.181 USAT
C2.182 USAT16
C2.183 USAX
C2.184 USUB8
C2.185 USUB16
C2.186 UXTAB
C2.187 UXTAB16
C2.188 UXTAH
C2.189 UXTB
C2.190 UXTB16
C2.191 UXTH
C2.192 WFE
C2.193 WFI
C2.194 YIELD
C3 Advanced SIMD Instructions (32-bit)
C3.1 Summary of Advanced SIMD instructions
C3.2 Summary of shared Advanced SIMD and floating-point instructions
C3.3 Interleaving provided by load and store element and structure instructions
C3.4 Alignment restrictions in load and store element and structure instructions
C3.5 FLDMDBX, FLDMIAX
C3.6 FSTMDBX, FSTMIAX
C3.7 VABA and VABAL
C3.8 VABD and VABDL
C3.9 VABS
C3.10 VACLE, VACLT, VACGE and VACGT
C3.11 VADD
C3.12 VADDHN
C3.13 VADDL and VADDW
C3.14 VAND (immediate)
C3.15 VAND (register)
C3.16 VBIC (immediate)
C3.17 VBIC (register)
C3.18 VBIF
C3.19 VBIT
C3.20 VBSL
C3.21 VCADD
C3.22 VCEQ (immediate #0)
C3.23 VCEQ (register)
C3.24 VCGE (immediate #0)
C3.25 VCGE (register)
C3.26 VCGT (immediate #0)
C3.27 VCGT (register)
C3.28 VCLE (immediate #0)
C3.29 VCLS
C3.30 VCLE (register)
C3.31 VCLT (immediate #0)
C3.32 VCLT (register)
C3.33 VCLZ
C3.34 VCMLA
C3.35 VCMLA (by element)
C3.36 VCNT
C3.37 VCVT (between fixed-point or integer, and floating-point)
C3.38 VCVT (between half-precision and single-precision floating-point)
C3.39 VCVT (from floating-point to integer with directed rounding modes)
C3.40 VCVTB, VCVTT (between half-precision and double-precision)
C3.41 VDUP
C3.42 VEOR
C3.43 VEXT
C3.44 VFMA, VFMS
C3.45 VFMAL (by scalar)
C3.46 VFMAL (vector)
C3.47 VFMSL (by scalar)
C3.48 VFMSL (vector)
C3.49 VHADD
C3.50 VHSUB
C3.51 VLDn (single n-element structure to one lane)
C3.52 VLDn (single n-element structure to all lanes)
C3.53 VLDn (multiple n-element structures)
C3.54 VLDM
C3.55 VLDR
C3.56 VLDR (post-increment and pre-decrement)
C3.57 VLDR pseudo-instruction
C3.58 VMAX and VMIN
C3.59 VMAXNM, VMINNM
C3.60 VMLA
C3.61 VMLA (by scalar)
C3.62 VMLAL (by scalar)
C3.63 VMLAL
C3.64 VMLS (by scalar)
C3.65 VMLS
C3.66 VMLSL
C3.67 VMLSL (by scalar)
C3.68 VMOV (immediate)
C3.69 VMOV (register)
C3.70 VMOV (between two general-purpose registers and a 64-bit extension register)
C3.71 VMOV (between a general-purpose register and an Advanced SIMD scalar)
C3.72 VMOVL
C3.73 VMOVN
C3.74 VMOV2
C3.75 VMRS
C3.76 VMSR
C3.77 VMUL
C3.78 VMUL (by scalar)
C3.79 VMULL
C3.80 VMULL (by scalar)
C3.81 VMVN (register)
C3.82 VMVN (immediate)
C3.83 VNEG
C3.84 VORN (register)
C3.85 VORN (immediate)
C3.86 VORR (register)
C3.87 VORR (immediate)
C3.88 VPADAL
C3.89 VPADD
C3.90 VPADDL
C3.91 VPMAX and VPMIN
C3.92 VPOP
C3.93 VPUSH
C3.94 VQABS
C3.95 VQADD
C3.96 VQDMLAL and VQDMLSL (by vector or by scalar)
C3.97 VQDMULH (by vector or by scalar)
C3.98 VQDMULL (by vector or by scalar)
C3.99 VQMOVN and VQMOVUN
C3.100 VQNEG
C3.101 VQRDMULH (by vector or by scalar)
C3.102 VQRSHL (by signed variable)
C3.103 VQRSHRN and VQRSHRUN (by immediate)
C3.104 VQSHL (by signed variable)
C3.105 VQSHL and VQSHLU (by immediate)
C3.106 VQSHRN and VQSHRUN (by immediate)
C3.107 VQSUB
C3.108 VRADDHN
C3.109 VRECPE
C3.110 VRECPS
C3.111 VREV16, VREV32, and VREV64
C3.112 VRHADD
C3.113 VRSHL (by signed variable)
C3.114 VRSHR (by immediate)
C3.115 VRSHRN (by immediate)
C3.116 VRINT
C3.117 VRSQRTE
C3.118 VRSQRTS
C3.119 VRSRA (by immediate)
C3.120 VRSUBHN
C3.121 VSDOT (vector)
C3.122 VSDOT (by element)
C3.123 VSHL (by immediate)
C3.124 VSHL (by signed variable)
C3.125 VSHLL (by immediate)
C3.126 VSHR (by immediate)
C3.127 VSHRN (by immediate)
C3.128 VSLI
C3.129 VSRA (by immediate)
C3.130 VSRI
C3.131 VSTM
C3.132 VSTn (multiple n-element structures)
C3.133 VSTn (single n-element structure to one lane)
C3.134 VSTR
C3.135 VSTR (post-increment and pre-decrement)
C3.136 VSUB
C3.137 VSUBHN
C3.138 VSUBL and VSUBW
C3.139 VSWP
C3.140 VTBL and VTBX
C3.141 VTRN
C3.142 VTST
C3.143 VUDOT (vector)
C3.144 VUDOT (by element)
C3.145 VUZP
C3.146 VZIP
C4 Floating-point Instructions (32-bit)
C4.1 Summary of floating-point instructions
C4.2 VABS (floating-point)
C4.3 VADD (floating-point)
C4.4 VCMP, VCMPE
C4.5 VCVT (between single-precision and double-precision)
C4.6 VCVT (between floating-point and integer)
C4.7 VCVT (from floating-point to integer with directed rounding modes)
C4.8 VCVT (between floating-point and fixed-point)
C4.9 VCVTB, VCVTT (half-precision extension)
C4.10 VCVTB, VCVTT (between half-precision and double-precision)
C4.11 VDIV
C4.12 VFMA, VFMS, VFNMA, VFNMS (floating-point)
C4.13 VJCVT
C4.14 VLDM (floating-point)
C4.15 VLDR (floating-point)
C4.16 VLDR (post-increment and pre-decrement, floating-point)
C4.17 VLLDM
C4.18 VLSTM
C4.19 VMAXNM, VMINNM (floating-point)
C4.20 VMLA (floating-point)
C4.21 VMLS (floating-point)
C4.22 VMOV (floating-point)
C4.23 VMOV (between one general-purpose register and single precision floating-point register)
C4.24 VMOV (between two general-purpose registers and one or two extension registers)
C4.25 VMOV (between a general-purpose register and half a double precision floating-point register)
C4.26 VMRS (floating-point)
C4.27 VMSR (floating-point)
C4.28 VMUL (floating-point)
C4.29 VNEG (floating-point)
C4.30 VNMLA (floating-point)
C4.31 VNMLS (floating-point)
C4.32 VNMUL (floating-point)
C4.33 VPOP (floating-point)
C4.34 VPUSH (floating-point)
C4.35 VRINT (floating-point)
C4.36 VSEL
C4.37 VSQRT
C4.38 VSTM (floating-point)
C4.39 VSTR (floating-point)
C4.40 VSTR (post-increment and pre-decrement, floating-point)
C4.41 VSUB (floating-point)
C5 A32/T32 Cryptographic Algorithms
C5.1 A32/T32 Cryptographic instructions

List of Figures

A1-1 Organization of general-purpose registers and Program Status Registers
B1-1 Extension register bank for Advanced SIMD in AArch32 state
B2-1 Extension register bank for floating-point in AArch32 state
C2-1 ASR #3
C2-2 LSR #3
C2-3 LSL #3
C2-4 ROR #3
C2-5 RRX
C3-1 De-interleaving an array of 3-element structures
C3-2 Operation of doubleword VEXT for imm = 3
C3-3 Example of operation of VPADAL (in this case for data type S16)
C3-4 Example of operation of VPADD (in this case, for data type I16)
C3-5 Example of operation of doubleword VPADDL (in this case, for data type S16)
C3-6 Operation of quadword VSHL.I64 Qd, Qm, #1
C3-7 Operation of quadword VSLI.64 Qd, Qm, #1
C3-8 Operation of doubleword VSRI.64 Dd, Dm, #2
C3-9 Operation of doubleword VTRN.8
C3-10 Operation of doubleword VTRN.32

List of Tables

A1-1 AArch32 processor modes
A1-2 Predeclared core registers in AArch32 state
A1-3 Predeclared extension registers in AArch32 state
A1-4 A32 instruction groups
B1-1 Advanced SIMD data types
B1-2 Advanced SIMD saturation ranges
C1-1 Condition code suffixes
C1-2 Condition code suffixes and related flags
C1-3 Condition codes
C1-4 Conditional branches only
C1-5 All instructions conditional
C2-1 Summary of instructions
C2-2 PC-relative offsets
C2-3 Register-relative offsets
C2-4 B instruction availability and range
C2-5 BL instruction availability and range
C2-6 BLX instruction availability and range
C2-7 BX instruction availability and range
C2-8 BXJ instruction availability and range
C2-9 Permitted instructions inside an IT block
C2-10 Offsets and architectures, LDR, word, halfword, and byte
C2-11 PC-relative offsets
C2-12 Options and architectures, LDR (register offsets)
C2-13 Register-relative offsets
C2-14 Offsets and architectures, LDR (User mode)
C2-15 Offsets and architectures, STR, word, halfword, and byte
C2-16 Options and architectures, STR (register offsets)
C2-17 Offsets and architectures, STR (User mode)
C3-1 Summary of Advanced SIMD instructions
C3-2 Summary of shared Advanced SIMD and floating-point instructions
C3-3 Patterns for immediate value in VBIC (immediate)
C3-4 Permitted combinations of parameters for VLDn (single n-element structure to one lane)
C3-5 Permitted combinations of parameters for VLDn (single n-element structure to all lanes)
C3-6 Permitted combinations of parameters for VLDn (multiple n-element structures)
C3-7 Available immediate values in VMOV (immediate)
C3-8 Available immediate values in VMVN (immediate)
C3-9 Patterns for immediate value in VORR (immediate)
C3-10 Available immediate ranges in VQRSHRN and VQRSHRUN (by immediate)
C3-11 Available immediate ranges in VQSHL and VQSHLU (by immediate)
C3-12 Available immediate ranges in VQSHRN and VQSHRUN (by immediate)
C3-13 Results for out-of-range inputs in VRECPE
C3-14 Results for out-of-range inputs in VRECPS
C3-15 Available immediate ranges in VRSHR (by immediate)
C3-16 Available immediate ranges in VRSHRN (by immediate)
C3-17 Results for out-of-range inputs in VRSQRTE
C3-18 Results for out-of-range inputs in VRSQRTS
C3-19 Available immediate ranges in VRSRA (by immediate)
C3-20 Available immediate ranges in VSHL (by immediate)
C3-21 Available immediate ranges in VSHLL (by immediate)
C3-22 Available immediate ranges in VSHR (by immediate)
C3-23 Available immediate ranges in VSHRN (by immediate)
C3-24 Available immediate ranges in VSRA (by immediate)
C3-25 Permitted combinations of parameters for VSTn (multiple n-element structures)
C3-26 Permitted combinations of parameters for VSTn (single n-element structure to one lane)
C3-27 Operation of doubleword VUZP.8
C3-28 Operation of quadword VUZP.32
C3-29 Operation of doubleword VZIP.8
C3-30 Operation of quadword VZIP.32
C4-1 Summary of floating-point instructions
C5-1 Summary of A32/T32 cryptographic instructions

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