ARM® Cortex®-A72 MPCore Processor Technical Reference Manual

Revision r0p1

Table of Contents

About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback on this product
Feedback on content
1 Introduction
1.1 About the Cortex-A72 processor
1.2 Compliance
1.2.1 ARM architecture
1.2.2 Advanced Microcontroller Bus Architecture (AMBA)
1.2.3 CHI architecture
1.2.4 Generic Interrupt Controller architecture
1.2.5 Generic Timer architecture
1.2.6 Debug architecture
1.2.7 Embedded Trace Macrocell architecture
1.3 Features
1.4 Interfaces
1.5 Implementation options
1.6 Test features
1.7 Product documentation and design flow
1.7.1 Documentation
1.7.2 Design flow
1.8 Product revisions
2 Functional Description
2.1 About the Cortex-A72 processor functions
2.1.1 Components of the processor
2.2 Interfaces
2.2.1 Memory interface
2.2.2 Optional Accelerator Coherency Port
2.2.3 Optional GIC CPU interface
2.2.4 Debug interface
2.2.5 Trace interface
2.2.6 PMU interface
2.2.7 Generic Timer interface
2.2.8 Cross trigger interface
2.2.9 Power management interface
2.2.10 DFT
2.2.11 MBIST
2.3 Clocking and resets
2.3.1 Clocks
2.3.2 Resets
2.4 Power management
2.4.1 Dynamic power management
2.4.2 Power domains
2.4.3 Power modes
2.4.4 Using SMPEN as a power mode indicator
3 Programmers Model
3.1 About the programmers model
3.2 ARMv8-A architecture concepts
3.2.1 Execution state
3.2.2 Exception levels
3.2.3 Security state
3.2.4 Rules for changing Exception state
3.2.5 Stack Pointer selection
3.2.6 ARMv8 security model
3.2.7 Instruction set state
3.2.8 AArch32 execution modes
3.3 ThumbEE instruction set
3.4 Jazelle implementation
3.4.1 Register summary
3.4.2 Register description
3.5 Memory model
4 System Control
4.1 About system control
4.1.1 Registers affected by CP15SDISABLE
4.2 AArch64 register summary
4.2.1 AArch64 identification registers
4.2.2 AArch64 exception handling registers
4.2.3 AArch64 virtual memory control registers
4.2.4 AArch64 other System registers
4.2.5 AArch64 cache maintenance operations
4.2.6 AArch64 TLB maintenance operations
4.2.7 AArch64 address translation operations
4.2.8 AArch64 miscellaneous operations
4.2.9 AArch64 Performance Monitors registers
4.2.10 AArch64 reset registers
4.2.11 Security registers
4.2.12 AArch64 virtualization registers
4.2.13 AArch64 EL2 TLB maintenance operations
4.2.14 Generic Timer registers
4.2.15 AArch64 IMPLEMENTATION DEFINED registers
4.3 AArch64 register descriptions
4.3.1 Main ID Register, EL1
4.3.2 Multiprocessor Affinity Register, EL1
4.3.3 Revision ID Register, EL1
4.3.4 AArch32 Processor Feature Register 0, EL1
4.3.5 AArch32 Processor Feature Register 1, EL1
4.3.6 AArch32 Debug Feature Register 0, EL1
4.3.7 AArch32 Auxiliary Feature Register 0, EL1
4.3.8 AArch32 Memory Model Feature Register 0, EL1
4.3.9 AArch32 Memory Model Feature Register 1, EL1
4.3.10 AArch32 Memory Model Feature Register 2, EL1
4.3.11 AArch32 Memory Model Feature Register 3, EL1
4.3.12 AArch32 Instruction Set Attribute Register 0, EL1
4.3.13 AArch32 Instruction Set Attribute Register 1, EL1
4.3.14 AArch32 Instruction Set Attribute Register 2, EL1
4.3.15 AArch32 Instruction Set Attribute Register 3, EL1
4.3.16 AArch32 Instruction Set Attribute Register 4, EL1
4.3.17 AArch32 Instruction Set Attribute Register 5, EL1
4.3.18 AArch64 Processor Feature Register 0, EL1
4.3.19 AArch64 Debug Feature Register 0, EL1
4.3.20 AArch64 Instruction Set Attribute Register 0, EL1
4.3.21 AArch64 Memory Model Feature Register 0, EL1
4.3.22 Cache Size ID Register, EL1
4.3.23 Cache Level ID Register, EL1
4.3.24 Auxiliary ID Register, EL1
4.3.25 Cache Size Selection Register, EL1
4.3.26 Cache Type Register, EL0
4.3.27 Data Cache Zero ID, EL0
4.3.28 Virtualization Processor ID Register, EL2
4.3.29 Virtualization Multiprocessor ID Register, EL2
4.3.30 System Control Register, EL1
4.3.31 Auxiliary Control Register, EL1
4.3.32 Architectural Feature Access Control Register, EL1
4.3.33 Auxiliary Control Register, EL2
4.3.34 Hypervisor Configuration Register, EL2
4.3.35 Architectural Feature Trap Register, EL2
4.3.36 Hypervisor System Trap Register
4.3.37 Hyp Auxiliary Configuration Register
4.3.38 System Control Register, EL3
4.3.39 Auxiliary Control Register, EL3
4.3.40 Architectural Feature Trap Register, EL3
4.3.41 Translation Control Register, EL1
4.3.42 Translation Control Register, EL2
4.3.43 Virtualization Translation Control Register, EL2
4.3.44 Translation Table Base Register 0, EL1
4.3.45 Translation Table Base Register 0, EL3
4.3.46 Translation Table Base Register 1, EL1
4.3.47 Translation Control Register, EL3
4.3.48 Auxiliary Fault Status Register 0, EL1 and EL3
4.3.49 Auxiliary Fault Status Register 1, EL1 and EL3
4.3.50 Exception Syndrome Register, EL1 and EL3
4.3.51 Instruction Fault Status Register, EL2
4.3.52 Auxiliary Fault Status Register 0, EL2 and Hyp Auxiliary Data Fault Status Register
4.3.53 Auxiliary Fault Status Register 1, EL2 and Hyp Auxiliary Instruction Fault Status Register
4.3.54 Exception Syndrome Register, EL2
4.3.55 Physical Address Register, EL1
4.3.56 Auxiliary Memory Attribute Indirection Register, EL1 and EL3
4.3.57 Auxiliary Memory Attribute Indirection Register, EL2
4.3.58 L2 Control Register, EL1
4.3.59 L2 Extended Control Register, EL1
4.3.60 Reset Vector Base Address, EL3
4.3.61 Reset Management Register, EL3
4.3.62 Instruction L1 Data n Register, EL1
4.3.63 Data L1 Data n Register, EL1
4.3.64 RAM Index operation
4.3.65 L2 Auxiliary Control Register, EL1
4.3.66 CPU Auxiliary Control Register, EL1
4.3.67 CPU Extended Control Register, EL1
4.3.68 CPU Memory Error Syndrome Register, EL1
4.3.69 L2 Memory Error Syndrome Register, EL1
4.3.70 Configuration Base Address Register, EL1
4.4 AArch32 register summary
4.4.1 c0 registers
4.4.2 c1 registers
4.4.3 c2 registers
4.4.4 c3 registers
4.4.5 c5 registers
4.4.6 c6 registers
4.4.7 c7 register
4.4.8 c7 System operations
4.4.9 c8 System operations
4.4.10 c9 registers
4.4.11 c10 registers
4.4.12 c12 registers
4.4.13 c13 registers
4.4.14 c14 registers
4.4.15 c15 registers
4.4.16 64-bit registers
4.4.17 Identification registers
4.4.18 CPUID registers
4.4.19 Virtual memory control registers
4.4.20 Fault and Exception handling registers
4.4.21 Other System registers
4.4.22 Cache maintenance operations
4.4.23 TLB maintenance operations
4.4.24 Address translation operations
4.4.25 Miscellaneous operations
4.4.26 Performance Monitors registers
4.4.27 Security registers
4.4.28 Virtualization registers
4.4.29 Hyp mode TLB maintenance operations
4.4.30 Generic Timer registers
4.4.31 Implementation defined registers
4.5 AArch32 register descriptions
4.5.1 TCM Type Register
4.5.2 TLB Type Register
4.5.3 Multiprocessor Affinity Register
4.5.4 Virtualization Multiprocessor ID Register
4.5.5 System Control Register
4.5.6 Architectural Feature Access Control Register
4.5.7 Secure Configuration Register
4.5.8 Non-secure Access Control Register
4.5.9 Secure Debug Configuration Register
4.5.10 Hyp Configuration Register
4.5.11 Hyp Configuration Register 2
4.5.12 Hyp Debug Control Register
4.5.13 Hyp Architectural Feature Trap Register
4.5.14 Translation Table Base Register 0 and Register 1
4.5.15 Translation Table Base Control Register
4.5.16 Hyp Translation Control Register
4.5.17 Data Fault Status Register
4.5.18 Physical Address Register
4.5.19 Primary Region Remap Register
4.5.20 Memory Attribute Indirection Register 0
4.5.21 Normal Memory Remap Register.
4.5.22 Memory Attribute Indirection Register 1
4.5.23 FCSE Process ID Register
4.5.24 Configuration Base Address Register
5 Memory Management Unit
5.1 About the MMU
5.2 TLB organization
5.2.1 L1 instruction TLB
5.2.2 L1 data TLB
5.2.3 L2 TLB
5.3 TLB match process
5.4 Memory access sequence
5.5 MMU enabling and disabling
5.6 Intermediate table walk caches
5.7 External aborts
5.7.1 External aborts on data read or write
5.7.2 Synchronous and asynchronous aborts
6 Level 1 Memory System
6.1 About the L1 memory system
6.2 Cache organization
6.3 L1 instruction memory system
6.3.1 Instruction cache disabled behavior
6.3.2 Instruction cache speculative memory accesses
6.3.3 Fill buffers
6.3.4 Non-cacheable fetching
6.3.5 Parity error handling
6.3.6 Hardware L1 I-cache prefetching
6.4 L1 data memory system
6.4.1 Behavior for different memory types
6.4.2 Coherence
6.4.3 Cache disabled behavior
6.4.4 Non-cacheable streaming enhancement
6.4.5 Synchronization primitives
6.4.6 Load/Store unprivileged instructions
6.4.7 Preload instruction behavior
6.4.8 Error Correction Code
6.4.9 Load/store hardware prefetcher
6.5 Program flow prediction
6.5.1 Predicted and non-predicted instructions
6.5.2 Return stack predictions
6.5.3 Indirect predictor
6.5.4 Static predictor
6.5.5 Enabling program flow prediction
6.5.6 BTB invalidation and context switches
6.6 L1 RAM memories
7 Level 2 Memory System
7.1 About the L2 memory system
7.2 Cache organization
7.2.1 L2 cache bank structure
7.2.2 Strictly-enforced inclusion property with L1 data caches
7.2.3 Enabling and disabling the L2 cache
7.2.4 Error Correction Code
7.2.5 Register slice support for large cache sizes
7.3 L2 RAM memories
7.4 L2 cache prefetcher
7.5 Cache coherency
7.6 Asynchronous errors
7.7 External coherent interfaces
7.7.1 L2 memory interface attributes
7.7.2 Interface modes
7.7.3 Snoop filter support
7.7.4 Distributed virtual memory transactions
7.7.5 External memory attributes
7.7.6 ACE ARID and AWID assignment
7.7.7 CHI LPID assignment
7.7.8 ACE supported transfers
7.7.9 CHI link layer flow control
7.7.10 CHI DVM acceptance capability
7.7.11 L2 Auxiliary Control Register settings
7.8 ACP
7.8.1 Transfer size support
7.8.2 ACP ARUSER and AWUSER signals
8 Generic Interrupt Controller CPU Interface
8.1 About the GIC
8.2 GIC functional description
8.2.1 GIC memory map
8.2.2 Interrupt sources
8.2.3 Interrupt priority levels
8.2.4 GIC bypass modes
8.2.5 nIRQ and nVFIQ inputs
8.3 GIC programmers model
8.3.1 CPU interface register summary
8.3.2 CPU interface memory-mapped register descriptions
8.3.3 CPU interface System register descriptions
8.3.4 Virtual interface control register summary
8.3.5 Virtual interface control register descriptions
8.3.6 Virtual CPU interface register summary
8.3.7 Virtual CPU interface register descriptions
9 Generic Timer
9.1 About the Generic Timer
9.2 Generic Timer functional description
9.3 Generic Timer register summary
9.3.1 AArch64 Generic Timer register summary
9.3.2 AArch32 Generic Timer register summary
10 Debug
10.1 About debug
10.1.1 Debug host
10.1.2 Protocol converter
10.1.3 Debug target
10.1.4 The debug unit
10.1.5 Self-hosted debug
10.2 Debug register interfaces
10.2.1 Processor interfaces
10.2.2 Breakpoints and watchpoints
10.2.3 Effects of resets on debug registers
10.2.4 External access permissions
10.3 AArch64 debug register summary
10.4 AArch64 debug register descriptions
10.4.1 Debug Breakpoint Control Registers, EL1
10.4.2 Debug Watchpoint Control Registers, EL1
10.5 AArch32 debug register summary
10.6 AArch32 debug register descriptions
10.6.1 Debug ID Register
10.6.2 Debug Device ID Register 1
10.6.3 Debug Device ID Register
10.7 Memory-mapped register summary
10.8 Memory-mapped register descriptions
10.8.1 External Debug Reserve Control Register
10.8.2 External Debug Auxiliary Control Register
10.8.3 External Debug Integration Output Control Register
10.8.4 External Debug Integration Input Status Register
10.8.5 External Debug Integration Mode Control Register
10.8.6 External Debug Device ID Register 1
10.8.7 External Debug Device ID Register 0
10.8.8 External Debug Peripheral Identification Registers
10.8.9 External Debug Component Identification Registers
10.9 Debug events
10.9.1 Watchpoint debug events
10.9.2 Debug OS Lock
10.10 External debug interface
10.10.1 Debug memory map
10.10.2 DBGPWRDUP debug signal
10.10.3 DBGL1RSTDISABLE debug signal
10.10.4 Changing the authentication signals
10.11 ROM table
10.11.1 ROM table register interface
10.11.2 ROM table register summary
10.11.3 ROM table register descriptions
10.11.4 ROM table Debug Peripheral Identification Registers
10.11.5 ROM table Debug Component Identification Registers
11 Performance Monitor Unit
11.1 About the PMU
11.2 PMU functional description
11.2.1 Event interface
11.2.2 System register and APB interface
11.2.3 Counters
11.2.4 PMU register interfaces
11.2.5 External register access permissions
11.3 AArch64 PMU register summary
11.4 AArch64 PMU register descriptions
11.4.1 Performance Monitors Control Register, EL0
11.4.2 Performance Monitors Common Event Identification Register 0, EL0
11.5 AArch32 PMU register summary
11.6 Memory-mapped register summary
11.7 Memory-mapped register descriptions
11.7.1 Performance Monitors Control Register, EL0
11.7.2 Performance Monitors Program Counter Sample Register
11.7.3 Performance Monitors Context ID Sample Register
11.7.4 Performance Monitors Virtual Context Sample Register
11.7.5 Performance Monitors Snapshot Status Register
11.7.6 Performance Monitors Overflow Status Snapshot Register
11.7.7 Performance Monitors Cycle Counter Snapshot Register
11.7.8 Performance Monitors Event Counters Snapshot Registers
11.7.9 Performance Monitors Snapshot Control Register
11.7.10 Performance Monitors Snapshot Reset Register
11.7.11 Performance Monitors Configuration Register
11.7.12 Performance Monitors Peripheral Identification Registers
11.7.13 Performance Monitors Component Identification Registers
11.8 Events
11.9 Interrupts
11.10 Exporting PMU events
11.10.1 External hardware
11.10.2 Debug trace hardware
12 Cross Trigger
12.1 About the cross trigger
12.2 Trigger inputs and outputs
12.3 CTI
12.4 CTM
12.5 Cross trigger register summary
12.5.1 External register access permissions
12.6 Cross trigger register descriptions
12.6.1 CTI Device Identification register
12.6.2 CTI Integration Mode Control register
12.6.3 CTI Integration Test Channel In Acknowledge register
12.6.4 CTI Integration Test Trigger In Acknowledge register
12.6.5 CTI Integration Test Channel Out register
12.6.6 CTI Integration Test Trigger Out register
12.6.7 CTI Integration Test Channel Out Acknowledge register
12.6.8 CTI Integration Test Trigger Out Acknowledge register
12.6.9 CTI Integration Test Channel In register
12.6.10 CTI Integration Test Trigger In register
12.6.11 CTI Peripheral Identification Registers
12.6.12 CTI Component Identification Registers
13 Embedded Trace Macrocell
13.1 About ETM
13.2 ETM trace generation options and resources
13.3 ETM functional description
13.4 Reset
13.5 ETM register interfaces
13.5.1 Access permissions
13.6 Register summary
13.7 Register descriptions
13.7.1 Trace Configuration Register
13.7.2 Trace Auxiliary Control Register
13.7.3 Trace Event Control 0 Register
13.7.4 Trace Event Control 1 Register
13.7.5 Trace Synchronization Period Register
13.7.6 Trace Cycle Count Control Register
13.7.7 Trace ID Register
13.7.8 ViewInst Main Control Register
13.7.9 External Input Select Register
13.7.10 ID Register 8
13.7.11 ID Register 9
13.7.12 ID Register 10
13.7.13 ID Register 11
13.7.14 ID Register 12
13.7.15 ID Register 13
13.7.16 Implementation Defined Register 0
13.7.17 Trace ID Register 0
13.7.18 Trace ID Register 1
13.7.19 Trace ID Register 2
13.7.20 Trace ID Register 3
13.7.21 Trace ID Register 4
13.7.22 Trace ID Register 5
13.7.23 Resource Selection Control Registers
13.7.24 Address Comparator Access Type Registers
13.7.25 Context ID Comparator Value Register 0
13.7.26 VMID Comparator Value Register 0
13.7.27 Context ID Comparator Control Register 0
13.7.28 Trace Integration Miscellaneous Outputs Register
13.7.29 Trace Integration Miscellaneous Input Register
13.7.30 Trace Integration Test ATB Data Register 0
13.7.31 Trace Integration Test ATB Control Register 2
13.7.32 Trace Integration Test ATB Control Register 1
13.7.33 Trace Integration Test ATB Control Register 0
13.7.34 Trace Integration Mode Control register
13.7.35 Trace Device Affinity register 0
13.7.36 Trace Device Affinity register 1
13.7.37 Trace Peripheral Identification Registers
13.7.38 Trace Component Identification Registers
13.8 Interaction with debug and the Performance Monitor Unit
13.8.1 Interaction with the Performance Monitor Unit
13.8.2 Effect of debug double lock on trace register access
14 Advanced SIMD and Floating-point
14.1 About Advanced SIMD and Floating-point
14.1.1 Advanced SIMD support
14.1.2 Floating-point support
14.2 Programmers model for Advanced SIMD and Floating-point
14.3 AArch64 register summary
14.4 AArch64 register descriptions
14.4.1 Floating-point Control Register
14.4.2 Floating-point Status Register
14.4.3 Media and VFP Feature Register 0, EL1
14.4.4 Media and VFP Feature Register 1, EL1
14.4.5 Media and VFP Feature Register 2, EL1
14.4.6 Floating-point Exception Control Register 32, EL2
14.5 AArch32 register summary
14.6 AArch32 register descriptions
14.6.1 Floating-point System ID Register
14.6.2 Floating-point Status and Control Register
A Signal Descriptions
A.1 About the signal descriptions
A.2 Clock signals
A.3 Reset signals
A.4 Configuration signals
A.5 GIC CPU interface signals
A.6 Generic Timer signals
A.7 Power control signals
A.8 ACE and CHI interface signals
A.8.1 Configuration signals
A.8.2 Asynchronous error signals
A.9 CHI interface signals
A.9.1 CHI clock and configuration signals
A.9.2 Transmit request virtual channel signals
A.9.3 Transmit response virtual channel signals
A.9.4 Transmit data virtual channel signals
A.9.5 Receive snoop virtual channel signals
A.9.6 Receive response virtual channel signals
A.9.7 Receive data virtual channel signals
A.9.8 System address map signals
A.10 ACE interface signals
A.10.1 Clock and configuration signals
A.10.2 Write address channel signals
A.10.3 Write data channel signals
A.10.4 Write response channel signals
A.10.5 Read address channel signals
A.10.6 Read data channel signals
A.10.7 Snoop address channel signals
A.10.8 Snoop response channel signals
A.10.9 Snoop data channel handshake signals
A.10.10 Read/Write acknowledge signals
A.11 ACP interface signals
A.11.1 Clock and configuration signals
A.11.2 Write address channel signals
A.11.3 Write data channel signals
A.11.4 Write response channel signals
A.11.5 Read address channel signals
A.11.6 Read data channel signals
A.12 Debug interface signals
A.12.1 APB interface signals
A.12.2 Authentication interface signals
A.12.3 Miscellaneous debug signals
A.13 ETM interface
A.13.1 ATB interface
A.13.2 Miscellaneous ETM signal
A.14 Cross trigger channel interface
A.15 PMU signals
A.16 DFT and MBIST signals
A.16.1 DFT signals
A.16.2 MBIST interface
B AArch32 Unpredictable Behaviors
B.1 Unpredictable behaviors
B.1.1 Use of R15 by instruction
B.1.2 Load or store accesses that span a page boundary
B.2 Debug UNPREDICTABLE behaviors
B.2.1 A32 BKPT instruction with condition code not AL
B.2.2 Address match breakpoint match only on second halfword of an instruction
B.2.3 Address matching breakpoint on A32 instruction with DBGBCRn.BAS=1100
B.2.4 Address match breakpoint match on T32 instruction at DBGBCRn+2 with DBGBCRn.BAS=1111
B.2.5 Address mismatch breakpoint match only on second halfword of an instruction
B.2.6 Address mismatch breakpoint match on T32 instruction at DBGBCRn+2 with DBGBCRn.BAS=1111
B.2.7 Other mismatch breakpoint matches any address in current mode and state
B.2.8 Mismatch breakpoint on branch to self
B.2.9 Link to nonexistent breakpoint or breakpoint that is not context-aware
B.2.10 DBGWCRn_EL1.MASK!=00000 and DBGWCRn_EL1.BAS!=11111111
B.2.11 Address-matching Vector catch on 32-bit T32 instruction at vector–2
B.2.12 Address-matching Vector catch on 32-bit T32 instruction at vector+2
B.2.13 Address-matching Vector catch and Breakpoint on same instruction
B.2.14 Address match breakpoint with DBGBCRn_EL1.BAS=0000
B.2.15 DBGWCRn_EL1.BAS specifies a non-contiguous set of bytes within a doubleword
B.2.16 A32 HLT instruction with condition code not AL
B.2.17 Execute instruction at a given EL when the corresponding EDECCR bit is 1 and Halting is allowed
B.2.18 Unlinked Context matching and Address mismatch breakpoints taken to Abort mode
B.2.19 Vector catch on Data or Prefetch Abort, and taken to Abort mode
B.2.20 H > N or H = 0 at Non-secure EL1 and EL0, including value read from PMCR_EL0.N
B.2.21 H > N or H = 0: value read back in MDCR_EL2.HPMN
B.2.22 P ≥ M and P ≠ 31: reads and writes of PMXEVTYPER_EL0 and PMXEVCNTR_EL0
B.2.23 P ≥ M and P ≠ 31: value read in PMSELR_EL0.SEL
B.2.24 P = 31: reads and writes of PMXEVCNTR_EL0
B.2.25 n ≥ M: Direct access to PMEVCNTRn_EL0 and PMEVTYPERn_EL0
B.2.26 Exiting Debug state while instruction issued through EDITR is in flight
B.2.27 Using memory-access mode with a non-word-aligned address
B.2.28 Access to memory-mapped registers mapped to Normal memory
B.2.29 Not word-sized accesses or (AArch64 only) doubleword-sized accesses
B.2.30 External debug write to register that is being reset
B.2.31 Accessing reserved debug registers
B.2.32 Clearing the clear-after-read EDPRSR bits when Core power domain is on, and DoubleLockStatus() is TRUE
C Revisions
C.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
0000-01 23 October 2014 Confidential First release for r0p0.
0000-02 20 February 2015 Non-Confidential First release for r0p1.

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