4.3.51 Instruction Fault Status Register, EL2

The IFSR32_EL2 characteristics are:
Purpose
Holds status information about the last instruction fault.
Usage constraints
The accessibility to the IFSR32_EL2 in AArch64 state by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- - - RW RW RW
The accessibility to the IFSR in AArch32 state by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- RW RW RW RW RW
Configurations
The IFSR32_EL2 is:
  • Banked for Secure and Non-secure states.
  • Mapped to the Non-secure AArch32 IFSR register.
Attributes
See the register summary in Table 4-2 AArch64 exception handling registers.
There are two formats for this register. The value of TTBCR.EAE selects which format of the register is used. The two formats are:
  • IFSR32_EL2 format when using the Short-descriptor translation table format.
  • IFSR32_EL2 format when using the Long-descriptor translation table format.
Related information
IFSR32_EL2 format when using the Short-descriptor translation table format
IFSR32_EL2 format when using the Long-descriptor translation table format

IFSR32_EL2 format when using the Short-descriptor translation table format

The following figure shows the IFSR32_EL2 bit assignments when using the Short-descriptor translation table format.
Figure 4-45 IFSR32_EL2 bit assignments for Short-descriptor translation table format
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The following table shows the IFSR32_EL2 bit assignments when using the Short-descriptor translation table format.

Table 4-62 IFSR32_EL2 bit assignments for Short-descriptor translation table format

Bits Name Function
[31:13] - Reserved, RES0.
[12] ExT
External abort type. This field indicates whether an AXI decode or slave error caused an abort. The possible values are:
0External abort marked as DECERR.
1External abort marked as SLVERR.
For aborts other than external aborts this bit always returns 0.
[11] - Reserved, RES0.
[10] FS[4] MSB of the Fault Status field. See bits[3:0] in this table.
[9] LPAE
Large physical address extension. The value of the format descriptor is:
0Short-descriptor translation table formats.
[8:4] - Reserved, RES0.
[3:0] FS[3:0]
Fault Status bits. This field indicates the type of exception generated. The possible values are:
0b00001Alignment fault.
0b01100Synchronous external abort on translation table walk, 1st level.
0b01110Synchronous external abort on translation table walk, 2nd level.
0b11100Synchronous parity error on translation table walk, 1st level.
0b11110Synchronous parity error on translation table walk, 2nd level.
0b00101Translation fault, 1st level.
0b00111Translation fault, 2nd level.
0b00011Access flag fault, 1st level.
0b00110Access flag fault, 2nd level.
0b01001Domain fault, 1st level.
0b01011Domain fault, 2nd level.
0b01101Permission fault, 1st level.
0b01111Permission fault, 2nd level.
0b00010Debug event.
0b01000Synchronous external abort, non-translation.
0b11001Synchronous parity error on memory access.
All other values are reserved.

IFSR32_EL2 format when using the Long-descriptor translation table format

The following figure shows the IFSR32_EL2 bit assignments when using the Long-descriptor translation table format.
Figure 4-46 IFSR32_EL2 bit assignments for Long-descriptor translation table format
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The following table shows the IFSR32_EL2 bit assignments when using the Long-descriptor translation table format.

Table 4-63 IFSR32_EL2 bit assignments for Long-descriptor translation table format

Bits Name Function
[31:13] - Reserved, res0.
[12] ExT
External abort type. This field indicates whether an AXI decode or slave error caused an abort. The possible values are:
0External abort marked as DECERR.
1External abort marked as SLVERR.
For aborts other than external aborts this bit always returns 0.
[11:10] - Reserved, res0.
[9] LPAE
Large physical address extension. The value of the format descriptor is:
1Long-descriptor translation table formats.
[8:6] - Reserved, res0.
[5:0] Status
Fault Status bits. This field indicates the type of exception generated. The possible values are:
0b0000LLAddress size fault, LL bits indicate level.
0b0001LLTranslation fault, LL bits indicate level.
0b0010LLAccess flag fault, LL bits indicate level.
0b0011LLPermission fault, LL bits indicate level.
0b010000Synchronous external abort.
0b011000Synchronous parity error on memory access.
0b0101LLSynchronous external abort on translation table walk, LL bits indicate level.
0b0111LLSynchronous parity error on memory access on translation table walk, LL bits indicate level.
0b100001Alignment fault.
0b100010Debug event.
All other values are reserved.
The following table shows how the LL bits in the Status field encode the lookup level associated with the MMU fault.

Table 4-64 Encodings of LL bits associated with the MMU fault

LL bits Meaning
00 Level 0
01 First level
10 Second level
11 Third level

Note

If a Data Abort exception is generated by an Instruction Cache maintenance operation, the fault is reported as a Cache Maintenance fault in the DFSR or HSR with the appropriate Fault Status code. For such exceptions reported in the DFSR, the corresponding IFSR is UNKNOWN.
To access the IFSR32_EL2 in AArch64 state, read or write the register with:
MRS <Xt>, IFSR32_EL2; Read EL2 Instruction Fault Status Register
MSR IFSR32_EL2, <Xt>; Write EL2 Instruction Fault Status Register
To access the IFSR in AArch32 state, read or write the CP15 register with:
MRC p15, 0, <Rt>, c5, c0, 1; Read Instruction Fault Status Register
MCR p15, 0, <Rt>, c5, c0, 1; Write Instruction Fault Status Register
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