10.11.3 ROM table register descriptions

This section describes the ROM table registers. 10.11.2  ROM table register summary provides cross-references to individual registers.

ROM entry registers

The characteristics of the ROMENTRYn are:

PurposeIndicates to a debugger whether the debug component is present in the processor's debug logic. There are 16 ROMENTRY registers in the Cortex-A72 processor.
Usage constraints
The accessibility to the ROMENTRYn by condition code is:
- - - - - RO
Table 11-1 External register access conditions describes the access conditions.
ConfigurationsThe ROMENTRYn is Common to Secure and Non-secure states.
AttributesSee the register summary in Table 10-30 ROM table registers.
The following figure shows the ROMENTRY bit assignments.
Figure 10-24 ROMENTRY bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The following table shows the ROMENTRY bit assignments.

Table 10-31 ROMENTRY bit assignments

Bits Name Function
[31:12] Address offset
Address offset for the debug component.


Negative values of address offsets are permitted using the two’s complement of the offset.
[11:2] - Reserved, RES0.
[1] Format
Format of the ROM table entry. The value for all ROMENTRY registers is:
0End marker.
132-bit format.
[0] Component presenta
Indicates whether the component is present:
0Component is not present.
1Component is present.
The Physical Address of a debug component is determined by shifting the address offset 12 places to the left and adding the result to Physical Address of processor ROM table.
The following table shows the offset values for all ROMENTRY values. If a processor is not implemented, the ROMENTRY registers for its debug, CTI, PMU, and ETM components are 0x00000000.

Table 10-32 ROMENTRY values

Name Debug component Offset value ROMENTRY value
ROMENTRY0 Core 0 Debug 0x00010 0x00010003
ROMENTRY1 Core 0 CTI 0x00020 0x00020003
ROMENTRY2 Core 0 PMU 0x00030 0x00030003
ROMENTRY3 Core 0 ETM 0x00040 0x00040003
ROMENTRY4 Core 1 Debug 0x00110 0x00110003
ROMENTRY5 Core 1 CTI 0x00120 0x00120003b
ROMENTRY6 Core 1 PMU 0x00130 0x00130003b
ROMENTRY7 Core 1 ETM 0x00140 0x00140003b
ROMENTRY8 Core 2 Debug 0x00210 0x00210003b
ROMENTRY9 Core 2 CTI 0x00220 0x00220003b
ROMENTRY10 Core 2 PMU 0x00230 0x00230003b
ROMENTRY11 Core 2 ETM 0x00240 0x00240003b
ROMENTRY12 Core 3 Debug 0x00310 0x00310003b
ROMENTRY13 Core 3 CTI 0x00320 0x00320003b
ROMENTRY14 Core 3 PMU 0x00330 0x00330003b
ROMENTRY15 Core 3 ETM 0x00340 0x00340003b
core 0 is always present. The component entries for core 1, 2, and 3 depend on your configuration.
If the component is present.
Non-ConfidentialPDF file icon PDF versionARM 100095_0002_03_en
Copyright © 2014, 2015 ARM. All rights reserved.