3.2.2 Exception levels

The ARMv8 exception model defines Exception levels EL0-EL3, where:
  • EL0 has the lowest software execution privilege, and execution at EL0 is called unprivileged execution.
  • Increased values of n, from 1 to 3, indicate increased software execution privilege.
  • EL2 provides support for processor virtualization.
  • EL3 provides support for two security states.
The Cortex-A72 processor implements all the Exception levels, EL0-EL3, and supports both Execution states, AArch64 and AArch32, at each Exception level.
Execution can move between Exception levels only on taking an exception, or on returning from an exception:
  • On taking an exception, the Exception level either increases or remains the same. The Exception level cannot decrease on taking an exception.
  • On returning from an exception, the Exception level either decreases or remains the same. The Exception level cannot increase on returning from an exception.
The Exception level that execution changes to, or remains in, on taking an exception, is called the target Exception level of the exception and:
  • Every exception type has a target Exception level that is either:
    • Implicit in the nature of the exception.
    • Defined by configuration bits in the System registers.
  • An exception cannot target the EL0 Exception level.
Exception levels, and privilege levels, are defined within a particular Security state, and 3.2.6 ARMv8 security model describes the permitted combinations of Security state and Exception level.
Related information
3.2.3 Security state

Exception terminology

This section defines terms used to describe the navigation between Exception levels.
Terminology for taking an exception

An exception is generated when the processor first responds to an exceptional condition. The processor state at this time is the state the exception is taken from. The processor state immediately after taking the exception is the state the exception is taken to.
Terminology for returning from an exception

To return from an exception, the processor must execute an exception return instruction.The processor state when an exception return instruction is committed for execution is the state the exception returns from. The processor state immediately after the execution of that instruction is the state the exception returns to.
Exception level terminology

An Exception level, ELn, with a larger value of n than another Exception level, is described as being a higher Exception level than the other Exception level. For example, EL3 is a higher Exception level than EL1.
An Exception level with a smaller value of n than another Exception level is described as being a lower Exception level than the other Exception level. For example, EL0 is a lower Exception level than EL1.
An Exception level is described as:
Using AArch64
When execution in that Exception level is in AArch64 Execution state.
Using AArch32
When execution in that Exception level is in AArch32 Execution state.
Typical Exception level usage model

The architecture does not specify how software can use the different Exception levels but the following is a common usage model for the Exception levels:
EL0Applications.
EL1OS kernel and associated functions that are typically described as privileged.
EL2Hypervisor.
EL3Secure monitor.
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