10.8.9 External Debug Component Identification Registers

There are four read-only External Debug Component Identification Registers, Debug Component ID0 through Debug Component ID3. The following table shows these registers.

Table 10-24 Summary of the External Debug Component Identification Registers

Register Value Offset
Component ID0 0x0D 0xFF0
Component ID1 0x90 0xFF4
Component ID2 0x05 0xFF8
Component ID3 0xB1 0xFFC
The External Debug Component Identification Registers identify Debug as an ARM Debug Interface v5 component. The External Debug Component ID registers are:

External Debug Component Identification Register 0

The EDCIDR0 characteristics are:

Purpose
Provides information to identify an external debug component.
Usage constraints
Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:
Off DLK OSLK EDAD SLK Default
- - - - - RO
Table 11-1 External register access conditions describes the access conditions.
Configurations
The EDCIDR0 is in the Debug power domain.
Attributes
See 10.7 Memory-mapped register summary.
The following figure shows the EDCIDR0 bit assignments.
Figure 10-19 EDCIDR0 bit assignments
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The following table shows the EDCIDR0 bit assignments.

Table 10-25 EDCIDR0 bit assignments

Bits Name Function
[31:8] - Reserved, RES0.
[7:0] PRMBL_0
0x0DPreamble byte 0.

External Debug Component Identification Register 1

The EDCIDR1 characteristics are:

Purpose
Provides information to identify an external debug component.
Usage constraints
Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:
Off DLK OSLK EDAD SLK Default
- - - - - RO
Table 11-1 External register access conditions describes the access conditions.
Configurations
The EDCIDR1 is in the Debug power domain.
Attributes
See 10.7 Memory-mapped register summary.
The following figure shows the EDCIDR1 bit assignments.
Figure 10-20 EDCIDR1 bit assignments
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The following table shows the EDCIDR1 bit assignments.

Table 10-26 EDCIDR1 bit assignments

Bits Name Function
[31:8] - Reserved, RES0.
[7:4] CLASS
0x9Debug component.
[3:0] PRMBL_1
0x0Preamble.

External Debug Component Identification Register 2

The EDCIDR2 characteristics are:

Purpose
Provides information to identify an external debug component.
Usage constraints
Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:
Off DLK OSLK EDAD SLK Default
- - - - - RO
Table 11-1 External register access conditions describes the access conditions.
Configurations
The EDCIDR2 is in the Debug power domain.
Attributes
See 10.7 Memory-mapped register summary.
The following figure shows the EDCIDR2 bit assignments.
Figure 10-21 EDCIDR2 bit assignments
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The following table shows the EDCIDR2 bit assignments.

Table 10-27 EDCIDR2 bit assignments

Bits Name Function
[31:8] - Reserved, RES0.
[7:0] PRMBL_2
0x05Preamble byte 2.

External Debug Component Identification Register 3

The EDCIDR3 characteristics are:

Purpose
Provides information to identify an external debug component.
Usage constraints
Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:
Off DLK OSLK EDAD SLK Default
- - - - - RO
Table 11-1 External register access conditions describes the access conditions.
Configurations
The EDCIDR3 is in the Debug power domain.
Attributes
See 10.7 Memory-mapped register summary.
The following figure shows the EDCIDR3 bit assignments.
Figure 10-22 EDCIDR3 bit assignments
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The following table shows the EDCIDR3 bit assignments.

Table 10-28 EDCIDR3 bit assignments

Bits Name Function
[31:8] - Reserved, RES0.
[7:0] PRMBL_3
0xB1Preamble byte 3.
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