2.3.2 Resets

The Cortex-A72 processor has the following reset inputs:

nCPUPORESET[N:0]
Initializes the entire core logic, including Debug, ETM, breakpoint and watchpoint logic in the processor CLK domain. Each core has one nCPUPORESET reset input.
nCORERESET[N:0]
Initializes the entire core but excludes the Debug, ETM, breakpoint and watchpoint logic. Each core has one nCORERESET reset input.
nPRESETDBG
Initializes the shared Debug APB, CTI, and CTM logic in the PCLKDBG domain.
nL2RESET
Initializes the shared L2 memory system, GIC, and Timer logic.
nMBISTRESET
Performs an MBIST mode reset.
All resets are active-LOW inputs. The reset signals enable you to reset different areas of the processor independently. The following table shows the areas of the processor controlled by the various reset signals.

Table 2-1 Areas that the reset signals control

Reset signal Corea (CLK) Debug and ETM (CLK) Debug APB, CTI, and CTM (PCLKDBG) L2 memory system, shared GIC and Timer logic Individual processor GIC and Timer logic
nCPUPORESET Reset Reset - - Reset
nCORERESET Reset - - - Reset
nPRESETDBG - - Reset - -
nL2RESET - - - Reset Reset
The following table shows the valid reset combinations the processor supports. The core which is being reset is indicated by [n].

Table 2-2 Valid reset combinations

Reset combination Signals Value Description
Full powerup reset for the processor
nCPUPORESET[N:0]
nCORERESET[N:0]
nPRESETDBG
nL2RESET
nMBISTRESET
all = 0
all = 0
0
0
1
All logic is held in reset.
Individual core powerup reset with Debug (PCLKDBG) reset
nCPUPORESET[N:0]
nCORERESET[N:0]
nPRESETDBG
nL2RESET
nMBISTRESET
[n] = 0
[n] = 0b
0
1
1
Individual core in the CLK domain and Debug in the PCLKDBG domain are held in reset, so that the core and Debug PCLKDBG domain can be powered up.
All core and L2 reset with Debug (PCLKDBG) active
nCPUPORESET[N:0]
nCORERESET[N:0]
nPRESETDBG
nL2RESET
nMBISTRESET
all = 0
all = 0b
1
0
1
All cores and L2 are held in reset, so they can be powered up. This enables external debug over powerdown for all cores.
Individual core powerup reset with Debug (PCLKDBG) active
nCPUPORESET[N:0]
nCORERESET[N:0]
nPRESETDBG
nL2RESET
nMBISTRESET
[n] = 0
[n] = 0b
1
1
1
Individual core is held in reset, so that the core can be powered up. This enables external debug over powerdown for the processor that is held in reset.
All cores Warm reset
nCPUPORESET[N:0]
nCORERESET[N:0]
nPRESETDBG
nL2RESET
nMBISTRESET
all = 1
all = 0
1
1
1
All logic, excluding Debug and ETM (CLK and PCLKDBG) and L2, is held in reset. All breakpoints and watchpoints are retained.
All cores Warm reset and L2 reset
nCPUPORESET[N:0]
nCORERESET[N:0]
nPRESETDBG
nL2RESET
nMBISTRESET
all = 1
all = 0
1
0
1
All logic, excluding Debug and ETM (CLK and PCLKDBG), is held in reset. All breakpoints and watchpoints are retained.
Individual core Warm reset
nCPUPORESET[N:0]
nCORERESET[N:0]
nPRESETDBG
nL2RESET
nMBISTRESET
[n] = 1
[n] = 0
1
1
1
Individual core logic, excluding the ETM and Debug in the CLK domain, is held in reset. Breakpoints and watchpoints for that core are retained.
Debug (PCLKDBG) reset
nCPUPORESET[N:0]
nCORERESET[N:0]
nPRESETDBG
nL2RESET
nMBISTRESET
all = 1
all = 1
0
1
1
Debug in the PCLKDBG domain is held in reset, so that the Debug PCLKDBG domain can be powered up.
Run mode
nCPUPORESET[N:0]
nCORERESET[N:0]
nPRESETDBG
nL2RESET
nMBISTRESET
1
1
1
1
1
No logic is held in reset.

Note

  • nL2RESET resets the shared L2 memory system logic, GIC, and Generic Timer that is common to all cores. This reset must not assert while any individual processor is active.
  • nPRESETDBG resets the shared Debug, PCLKDBG, that is common to all cores. This reset must not assert while any individual core is actively being debugged in normal operating mode or during external debug over powerdown.
There are specific requirements that you must meet to reset each reset area listed in Table 2-1 Areas that the reset signals control. Not adhering to these requirements can lead to a reset area that is not functional.
The reset sequences in the following sections are the only reset sequences that ARM recommends. Any deviation from these sequences might cause an improper reset of that reset domain. The supported reset sequences are:

Powerup reset

Powerup reset is also known as Cold reset. This section describes the sequence for:
  • A full powerup reset.
  • An individual core powerup reset.
The full powerup reset initializes all logic in the processor. You must apply powerup reset to the processor when power is first applied to the SoC. Logic in all clock domains are placed in a benign state following the deassertion of the reset sequence.
The following figure shows the full powerup reset sequence for the Cortex-A72 processor.
Figure 2-8 Powerup reset timing
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On full powerup reset for the processor, perform the following reset sequence:
  1. Apply nCPUPORESET, nL2RESET, and nPRESETDBG. The remaining core reset, nCORERESET can assert, but is not required.
  2. nCPUPORESET and nL2RESET must assert for at least 16 CLK cycles. nPRESETDBG must assert for at least 16 PCLKDBG cycles. Holding the resets for this duration ensures that the resets propagate to all locations within the processor.
  3. nL2RESET must deassert in the same cycle as the core resets, or before any of the core resets deassert.
Individual core powerup reset initializes all logic in a single core. You must apply the powerup reset when the individual core is being powered up, so that power to the core can be safely applied. You must apply the correct sequence before applying a powerup reset to that core.
For individual core powerup reset:
  • nCPUPORESET for that core must assert for at least 16 CLK cycles.
  • nL2RESET must not assert while any individual core is active.
  • nPRESETDBG must not assert while any individual core is actively being debugged in normal operating mode or during external debug over powerdown.

Note

If core dynamic retention using the CPU Q-channel interface is used, the core must be in quiescent state with STANDBYWFI asserted and CPUQREQn, CPUQACCEPTn, and CPUQACCEPT must be LOW before nCPUPORESET is applied.

Warm reset

The Warm reset initializes all logic in the individual core apart from the Debug and ETM logic in the CLK domain. All breakpoints and watchpoints are retained during a Warm reset sequence.
The following figure shows the Warm reset sequence for the Cortex-A72 processor.
Figure 2-9 Warm reset timing
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Individual core Warm reset initializes all logic in a single core apart from its Debug, ETM, breakpoint, and watchpoint logic. Breakpoints and watchpoints for that core are retained. You must apply the correct sequence before applying Warm reset to that core.
For individual processor Warm reset:
  • You must apply steps 1 to 12 in the core powerdown sequence, see Individual core powerdown, and wait until STANDBYWFI is asserted, indicating that the core is idle, before asserting nCORERESET for that core.
  • nCORERESET for that core must assert for at least 16 CLK cycles.
  • nL2RESET must not assert while any individual core is active.
  • nPRESETDBG must not assert while any individual core is actively being debugged in normal operating mode.

Note

If core dynamic retention using the CPU Q-channel interface is used, the core must be in quiescent state with STANDBYWFI asserted and CPUQREQn, CPUQACCEPTn, and CPUQACCEPT must be LOW before nCORERESET is applied.

Debug PCLKDBG reset

Use nPRESETDBG to reset the Debug APB, CTI, and CTM logic in the PCLKDBG domain. This reset holds the Debug PCLKDBG unit in a reset state so that the power to the unit can be safely applied during powerup.
To safely reset the Debug PCLKDBG unit, nPRESETDBG must assert for a minimum of 16 PCLKDBG cycles.
The following figure shows the Debug PCLKDBG reset sequence.
Figure 2-10 Debug PCLKDBG reset timing
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WARMRSTREQ and DBGRSTREQ

The ARMv8-A architecture provides a mechanism to configure whether a processor uses AArch32 or AArch64 at EL3 as a result of a Warm reset. When the Reset Request bit in the RMR or RMR_EL3 register is set to 1, the processor asserts the WARMRSTREQ signal and the SoC reset controller can use this request to trigger a Warm reset of the core and change the register width state. The AA64 bit in the RMR or RMR_EL3 register selects the register width at the next Warm reset, at the highest Exception level, EL3.
See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for information about the recommended code sequence to use, to request a Warm reset.
You must apply steps 1 to 12 in the core powerdown sequence, and wait until STANDBYWFI asserts indicating the processor is idle, before asserting nCORERESET for that core. nCORERESET must satisfy the timing requirements described in the Warm reset section.
The Core Warm Reset Request (CWRR) bit in the External Debug Power/Reset Control Register, EDPRCR, controls the DBGRSTREQ signal. An external debugger can use this bit to request a Warm reset of the processor, if it does not have access to the core Warm reset signal. See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information about the EDPRCR.

Memory arrays reset

During a core reset, the following memory arrays in the core are invalidated:
  • Branch Prediction arrays such as BTB, GHB, and Indirect Predictor.
  • L1 instruction and data TLBs.
  • L1 instruction and data caches.
  • L2 unified TLB.
In addition to these core memory arrays, during a powerup reset, the following shareable memory arrays are invalidated:
  • L2 duplicate Snoop Tag RAM.
  • L2 unified cache RAM, if L2RSTDISABLE is tied LOW.
The L1 instruction and data cache resets can take up to 128 CLK cycles after the deasserting edge of the reset signals, with each array being reset in parallel. Depending on the size of the L2 cache, the L2 cache reset can take 640 CLK cycles for a 512KB L2 cache or 5120 CLK cycles for a 4MB L2 cache. The L2 cache reset occurs in the background, in parallel with the L1 cache resets. The core can begin execution in Non-cacheable state, but any attempt to perform Cacheable transactions stalls the core until the appropriate cache reset is complete.
The branch prediction arrays require 512 CLK cycles to reset after the deasserting edge of reset. The core begins execution with branch prediction disabled, any resolved branches do not update the branch predictor until the reset sequence completes.
The processor input signal, L2RSTDISABLE, controls the L2 cache hardware reset process. The usage models for the L2RSTDISABLE signal are as follows:
  • When the processor powers up for the first time, L2RSTDISABLE must be held LOW to invalidate the L2 cache using the L2 cache hardware reset mechanism.
  • For systems that do not retain the L2 cache RAM contents while the L2 memory system is powered down, L2RSTDISABLE must be held LOW to invalidate the L2 cache using the L2 cache hardware reset mechanism.
  • For systems that retain the L2 cache RAM contents while the L2 memory system is powered down, L2RSTDISABLE must be held HIGH to disable the L2 cache hardware reset mechanism.
The L2RSTDISABLE signal is sampled during nL2RESET assertion and must be held a minimum of 32 CLK cycles after the deasserting edge of nL2RESET.
a Core logic, excluding Debug, ETM, breakpoint, and watchpoint logic.
b For powerup reset or core reset, nCPUPORESET must be asserted. nCORERESET can be asserted, but is not required.
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