13.7.38 Trace Component Identification Registers

There are four read-only Trace Component Identification Registers, Trace Component ID0 to Trace Component ID3. The following table shows these registers.

Table 13-44 Summary of the ETM Component Identification Registers

Register Value Offset
TRCCIDR0 0x0D 0xFF0
TRCCIDR1 0x90 0xFF4
TRCCIDR2 0x05 0xFF8
TRCCIDR3 0xB1 0xFFC
The Trace Component Identification Registers identify ETM as a CoreSight component.
The Trace Component ID registers are:

Trace Component Identification Register 0

The TRCCIDR0 characteristics are:
Purpose
Provides information to identify a trace component.
Usage constraints
  • Only bits[7:0] are valid.
  • Accessible only from the memory-mapped interface or the external debugger interface.
Configurations
Available in all implementations.
Attributes
See 13.6 Register summary.
The following figure shows the TRCCIDR0 bit assignments.
Figure 13-41 TRCCIDR0 bit assignments
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The following table shows the TRCCIDR0 bit assignments.

Table 13-45 TRCCIDR0 bit assignments

Bits Name Function
[31:8] - Reserved, RES0.
[7:0] PRMBL_0
0x0DPreamble byte 0.
TRCCIDR0 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFF0.

Trace Component Identification Register 1

The TRCCIDR1 characteristics are:

Purpose
Provides information to identify a trace component.
Usage constraints
  • Only bits[7:0] are valid.
  • Accessible only from the memory-mapped interface or the external debugger interface.
Configurations
Available in all implementations.
Attributes
See 13.6 Register summary.
The following figure shows the TRCCIDR1 bit assignments.
Figure 13-42 TRCCIDR1 bit assignments
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The following table shows the TRCCIDR1 bit assignments.

Table 13-46 TRCCIDR1 bit assignments

Bits Name Function
[31:8] - Reserved, RES0.
[7:4] CLASS
0x9Debug component.
[3:0] PRMBL_1
0x0Preamble.
TRCCIDR1 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFF4.

Trace Component Identification Register 2

The TRCCIDR2 characteristics are:

Purpose
Provides information to identify a CTI component.
Usage constraints
  • Only bits[7:0] are valid.
  • Accessible only from the memory-mapped interface or the external debugger interface.
Configurations
Available in all implementations.
Attributes
See 13.6 Register summary.
The following figure shows the TRCCIDR2 bit assignments.
Figure 13-43 TRCCIDR2 bit assignments
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The following table shows the TRCCIDR2 bit assignments.

Table 13-47 TRCCIDR2 bit assignments

Bits Name Function
[31:8] - Reserved, RES0.
[7:0] PRMBL_2
0x05Preamble byte 2.
TRCCIDR2 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFF8.

Trace Component Identification Register 3

The TRCCIDR3 characteristics are:

Purpose
Provides information to identify a trace component.
Usage constraints
  • Only bits[7:0] are valid.
  • Accessible only from the memory-mapped interface or the external debugger interface.
Configurations
Available in all implementations.
Attributes
See 13.6 Register summary.
The following figure shows the TRCCIDR3 bit assignments.
Figure 13-44 TRCCIDR3 bit assignments
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The following table shows the TRCCIDR3 bit assignments.

Table 13-48 TRCCIDR3 bit assignments

Bits Name Function
[31:8] - Reserved, RES0.
[7:0] PRMBL_3
0xB1Preamble byte 3.
TRCCIDR3 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFFC.
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