8.3.7 Virtual CPU interface register descriptions

This section only describes registers whose implementation is specific to the Cortex-A72 processor.

All other registers are described in the ARM® Generic Interrupt Controller Architecture Specification, GICv3. Table 8-14 Virtual CPU interface register summary provides cross-references to individual registers.

VM Active Priority Register

The GICV_APR0 characteristics are:
Purpose
For software compatibility, this register is present in the virtual CPU interface. However, in virtualized system, it is not used in the preserving and restoring state.
Usage constraints
Reading the content of this register and then writing the same values must not change any state because there is no requirement to preserve and restore state during a power down.
Configurations
Available if the GIC is implemented.
Attributes
See the register summary in Table 8-14 Virtual CPU interface register summary.
The multiprocessor implements the GICV_APR0 as an alias of GICH_APR.

VM CPU Interface Identification Register

The GICV_IIDR characteristics are:
Purpose
Provides information about the implementer and revision of the virtual CPU interface.
Usage constraints
There are no usage constraints.
Configurations
Available if the GIC is implemented.
Attributes
See the register summary in Table 8-14 Virtual CPU interface register summary.
The bit assignments for the VM CPU Interface Identification Register are identical to the corresponding register in the CPU interface.
Non-ConfidentialPDF file icon PDF versionARM 100095_0002_03_en
Copyright © 2014, 2015 ARM. All rights reserved.