11.7.12 Performance Monitors Peripheral Identification Registers

The Performance Monitors Peripheral Identification Registers provide standard information required for all components that conform to the ARM PMUv3 architecture. There is a set of eight registers, listed in register number order in the following table.

Table 11-13 Summary of the Performance Monitors Peripheral Identification Registers

Register Value Offset
PMPIDR4 0x04 0xFD0
PMPIDR5 0x00 0xFD4
PMPIDR6 0x00 0xFD8
PMPIDR7 0x00 0xFDC
PMPIDR0 0xD8 0xFE0
PMPIDR1 0xB9 0xFE4
PMPIDR2 0x0B 0xFE8
PMPIDR3 0x00 0xFEC
Only bits[7:0] of each PMU Peripheral ID Register are used, with bits[31:8] reserved. Together, the eight PMU Peripheral ID Registers define a single 64-bit Peripheral ID.
The PMU Peripheral ID registers are:

Performance Monitors Peripheral Identification Register 0

The PMPIDR0 characteristics are:

Purpose
Provides information to identify a Performance Monitors component.
Usage constraints
The PMPIDR0 can be accessed through the internal memory-mapped interface and the external debug interface.
The accessibility to the PMPIDR0 by condition code is:
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
Table 11-1 External register access conditions describes the condition codes.
Configurations
The PMPIDR0 is in the Debug power domain.
Attributes
See the register summary in Table 11-7 Memory-mapped PMU register summary.
The following figure shows the PMPIDR0 bit assignments.
Figure 11-9 PMPIDR0 bit assignments
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The following table shows the PMPIDR0 bit assignments.

Table 11-14 PMPIDR0 bit assignments

Bits Name Function
[31:8] -
Reserved, RES0
[7:0] Part_0
0xD8Least significant byte of the performance monitor part number
The PMPIDR0 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFE0.

Performance Monitors Peripheral Identification Register 1

The PMPIDR1 characteristics are:
Purpose
Provides information to identify a Performance Monitors component.
Usage constraints
The PMPIDR1 can be accessed through the internal memory-mapped interface and the external debug interface.
The accessibility to the PMPIDR1 by condition code is:
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
Table 11-1 External register access conditions describes the condition codes.
Configurations
The PMPIDR1 is in the Debug power domain.
Attributes
See the register summary in Table 11-7 Memory-mapped PMU register summary.
The following figure shows the PMPIDR1 bit assignments.
Figure 11-10 PMPIDR1 bit assignments
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The following table shows the PMPIDR1 bit assignments.

Table 11-15 PMPIDR1 bit assignments

Bits Name Function
[31:8] -
Reserved, RES0.
[7:4] DES_0
0xBARM Limited. This is the least significant nibble of JEP106 ID code.
[3:0] Part_1
0x9Most significant nibble of the performance monitor part number.
The PMPIDR1 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFE4.

Performance Monitors Peripheral Identification Register 2

The PMPIDR2 characteristics are:

Purpose
Provides information to identify a Performance Monitors component.
Usage constraints
The accessibility to the PMPIDR2 by condition code is:
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
Table 11-1 External register access conditions describes the condition codes.
The PMPIDR2 can be accessed through the internal memory-mapped interface and the external debug interface.
Configurations
The PMPIDR2 is in the Debug power domain.
Attributes
See the register summary in Table 11-7 Memory-mapped PMU register summary.
The following figure shows the PMPIDR2 bit assignments.
Figure 11-11 PMPIDR2 bit assignments
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The following table shows the PMPIDR2 bit assignments.

Table 11-16 PMPIDR2 bit assignments

Bits Name Function
[31:8] -
Reserved, RES0.
[7:4] Revision
0Part major revision.
[3] JEDEC
0b1RAO. Indicates a JEP106 identity code is used.
[2:0] DES_1
0b011ARM Limited. This is the most significant nibble of JEP106 ID code.
The PMPIDR2 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFE8.

Performance Monitors Peripheral Identification Register 3

The PMPIDR3 characteristics are:
Purpose
Provides information to identify a Performance Monitors component.
Usage constraints
The PMPIDR3 can be accessed through the internal memory-mapped interface and the external debug interface.
The accessibility to the PMPIDR3 by condition code is:
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
Table 11-1 External register access conditions describes the condition codes.
Configurations
The PMPIDR3 is in the Debug power domain.
Attributes
See the register summary in Table 11-7 Memory-mapped PMU register summary.
The following figure shows the PMPIDR3 bit assignments.
Figure 11-12 PMPIDR3 bit assignments
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The following table shows the PMPIDR3 bit assignments.

Table 11-17 PMPIDR3 bit assignments

Bits Name Function
[31:8] -
Reserved, RES0
[7:4] REVAND
0x0Part minor revision
[3:0] CMOD
0x0Customer modified
The PMPIDR3 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFEC.

Performance Monitors Peripheral Identification Register 4

The PMPIDR4 characteristics are:

Purpose
Provides information to identify a Performance Monitors component.
Usage constraints
PMPIDR4 can be accessed through the internal memory-mapped interface and the external debug interface.
The accessibility to the PMPIDR4 by condition code is:
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
Table 11-1 External register access conditions describes the condition codes.
Configurations
The PMPIDR4 is in the Debug power domain.
Attributes
See the register summary in Table 11-7 Memory-mapped PMU register summary.
The following figure shows the PMPIDR4 bit assignments.
Figure 11-13 PMPIDR4 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The following table shows the PMPIDR4 bit assignments.

Table 11-18 PMPIDR4 bit assignments

Bits Name Function
[31:8] -
Reserved, RES0.
[7:4] Size
0x0Size of the component. Log2 the number of 4KB pages from the start of the component to the end of the component ID registers.
[3:0] DES_2
0x4ARM Limited. This is the least significant nibble JEP106 continuation code.
The PMPIDR4 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFD0.

Performance Monitors Peripheral Identification Register 5-7

No information is held in the Performance Monitors Peripheral ID5, Performance Monitors Peripheral ID6, and Performance Monitors Peripheral ID7 Registers. They are reserved for future use and are RES0.

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